1. Field of the Invention
The present invention relates to a capable semiconductor device such as a micromachine, a solar battery having a high energy conversion efficiency, a volatile or a nonvolatile memory, a load of a memory cell of an SRAM, a field effective thin film transistor (hereinafter referred to as xe2x80x9cTFTxe2x80x9d) which is used as a display device of a wide-screen, high-precision active-matrix type liquid crystal display and a liquid crystal display which comprises a pixel electrode and a thin film transistor. The present invention also relates to a method for manufacturing such a semiconductor device.
2. Background of the Invention
(Priot Art 1)
A prototype of a micromachine, which is typically an apparatus of fine dimensions in the units of micrometers or less having a mechanical motion mechanism, is prepared by redeployment of a semiconductor technique mainly implementing simultaneous formation on a semiconductor wafer by transfer of a mask pattern or the like.
 less than Micromachine Having Movable Part greater than 
FIG. 77 is a front sectional view showing a sectional structure of an electrostatic motor 3000 which is manufactured by a conventional method. In this electrostatic motor 3000, a nitride film (Si3N4 film) 3004 is formed on a single-crystalline Si substrate 3002, and a rotary shaft 3014 and a stator 3010 of polycrystalline Si are fixedly formed on the nitride film 3004, while a ring-shaped rotator 3008 of polycrystalline Si is stopped to the rotary shaft 3014 with a clearance. Thus, the rotator 3008 is rotatable about the rotary shaft 3014.
The stator 3010 is formed by a plurality of members, being electrically isolated from each other, which are radially arranged at prescribed intervals to enclose the rotator 3008. Alternating voltages which are out of phase with each other are independently applied to these members of the stator 3010. Consequently, electrostatic attractive or repulsive force is generated between the stator 3010 and the rotator 3008, and a bearer of such force is successively moved between the respective members, thereby rotating the rotator 3008. It is reported that the rotator 3008 is 100 xcexcm in diameter and 2.5 xcexcm in thickness.
FIG. 78 is a process diagram showing a certain stage in a method of manufacturing the electrostatic motor 3000. In manufacturing of the electrostatic motor 3000, a technique of forming sacrifice layers and etching the same is employed in order to isolate the rotator 3008, the stator 3010, the rotary shaft 3014 and the nitride film 3004 serving as an underlayer from each other and defining clearances therebetween. In order to manufacture the electrostatic motor 3000, an SiO2 layer is first temporarily formed on an upper surface of the nitride film 3004 and selectively removed to form a first sacrifice layer 3006, for selectively filling up spaces corresponding to clearances. A polycrystalline Si layer is stacked thereon by CVD (chemical vapor deposition) or the like. Thereafter this polycrystalline Si layer is selectively removed to be formed into the shapes of the rotator 3008 and the stator 3010. Another sacrifice layer 3012 is newly formed so that another polycrystalline Si layer is newly stacked thereon, whereafter this polycrystalline Si layer is selectively removed to be formed into the shape of the rotary shaft 3014. Finally, the two sacrifice layers 3006 and 3012 are entirely removed by etching, thereby completing the electrostatic motor 3000 shown in FIG. 77.
 less than Micromachine Having Deformed Part greater than 
FIG. 79 is a plan view showing an electrostatic linear actuator 3030 which is manufactured by a conventional method. In this actuator 3030, fixed electrodes 3040 of polycrystalline Si and movable parts 3036 of polycrystalline Si are formed on a single-crystalline Si substrate 3032. The comb-shaped fixed electrodes 3040 are fixed onto the single-crystalline Si substrate 3032 in base portions thereof, so that comb-shaped protrusions are upwardly raised from the single-crystalline Si substrate 3032. On the other hand, the movable parts 3036 are fixed to the single-crystalline Si substrate 3032 only in support portions 3034, so that other portions are entirely upwardly raised from the single-crystalline Si substrate 3032. The movable parts 3036 have comb-shaped forward end portions 3038, which are fitted with the fixed electrodes 3040 with no contact.
When voltages are applied to the fixed electrodes 3040, electrostatic attractive or repulsive force acts across the same and the forward end portions 3038, whereby the forward end portions 3038 are straightly displaced in a horizontal plane. At this time, members coupling the forward end portions 3038 with the support portions 3034, which are elastic members serving as sources of restoring force for the displacement of the forward end portions 3038, are elastically deformed following the displacement of the forward end portions 3038.
A method of manufacturing the actuator 3030 also employs a step of forming a sacrifice layer and removing the same by etching, similarly to the method of manufacturing the electrostatic motor 3000. Namely, a sacrifice layer is first formed on the single-crystalline Si substrate 3032, so that a polycrystalline Si layer is formed thereon. Thereafter the polycrystalline Si layer is selectively removed, to be formed into the shapes of the movable parts 3036 and the fixed electrodes 3040. Finally, the sacrifice layer is entirely removed by etching, to complete the actuator 3030.
 less than Micromachine Having Cavity greater than 
FIG. 80 is a fragmented perspective view showing a part of a pressure sensor 3100 which is manufactured by a conventional method. In this pressure sensor 3100, a lower housing 3102 and an upper housing 3104 having grooves are joined with each other to form a hollow vessel defining a cavity 3106 in its interior. A plate-type oscillator 3108 is inserted in this cavity 3106. All of the lower housing 3102, the upper housing 3104 and the oscillator 3108 are made of single-crystalline Si.
Only an end portion of the oscillator 3108 is in contact with an inner wall portion defining the cavity 3106 to be supported by the hollow vessel, while all of the remaining portions are separated from the inner walls. Therefore, it is possible to excite natural oscillation in the oscillator 3108 by applying a stationary magnetic field and an oscillating current from the exterior. The lower housing 3102 is coupled with a diaphragm (not shown) which receives a pressure to be measured. The diaphragm is deformed upon application of the pressure, whereby the oscillator 3108 is also deformed. Upon such deformation of the oscillator 3108, the natural frequency deviates in response to the degree of the displacement. The level of the pressure is measured by detecting the deviation of the natural frequency. This pressure sensor 3100 has an excellent elastic limit, excellent strength and the like, as well as uniform characteristics since all of the members 3102, 3104 and 3108 are made of single-crystalline Si. Therefore, it is possible to provide these members with large deformation, while implementing a pressure sensor having high reliability.
In order to manufacture the pressure sensor 3100, a technique of junction (also referred to as xe2x80x9ccladdingxe2x80x9d) is employed as hereinabove described. After the two housings 3102 and 3104 having grooves and the oscillator 3108 are prepared from single-crystalline Si independently of each other, the two housings 3102 and 3104 are joined with each other at a junction plane 3110 while receiving the oscillator 3108 in the grooves. This junction step is carried out in a vacuum, whereby the cavity 3106 is maintained in a vacuum state also after completion of the apparatus.
 less than Micromachine Having Diaphragm greater than 
FIG. 81 is a front elevational view showing another pressure sensor 3200 which is manufactured by a conventional method. Junction of single-crystalline Si is employed also in manufacturing of the pressure sensor 3200. Namely, a V-shaped groove 3204 is formed on a single-crystalline Si substrate 3202 by etching, whereafter a thin substrate 3206 of single-crystalline Si is joined thereto at a junction plane 3208. Thereafter etching is further advanced to expand the V-shaped groove 3204 to be opened in a bottom surface of the substrate 3202. The etching step is carried out with an etchant for selectively etching a specific crystal plane.
In the thin substrate 3206, a portion 3212 covering the groove 3204 serves as a diaphragm which receives a pressure to be measured. The diaphragm 3212 is elastically deformed by such application of the pressure. A piezoresistance element 3210 serving as a distortion gauge is formed in the vicinity of a portion having the maximum distortion following the elastic deformation, i.e., a fixed end of the diaphragm 3212. This piezoresistance element 3210 is formed by selectively implanting impurity ions into a specific portion of an upper surface of the diaphragm 3212. This pressure sensor 3200 is adapted to measure the value of the pressure through an amount of change in electric resistance in the piezoresistance element 3210. According to this pressure sensor 3200, large elastic deformation can be applied to the diaphragm 3212, since this diaphragm 3212 is made of single-crystalline Si.
 less than Micromachine Provided with Element on Insulating Layer greater than 
FIG. 82 is a front elevational view showing still another pressure sensor 3230 which is manufactured by a conventional method. Junction of single-crystalline Si is employed also in manufacturing of the pressure sensor 3230. Namely, an insulating film 3236 of SiO2 is first formed on a single-crystalline Si substrate 3232 having a diaphragm 3234 on a groove. Then, a single-crystalline Si thin film is joined onto this insulating film 3236. A p-type impurity is previously selectively introduced into this single-crystalline Si thin film, to form a piezoresistance element 3238 of p-type Si for serving as a distortion gauge. After completion of the junction, the single-crystalline Si thin film is etched for leaving the p-type Si portion while selectively removing the remaining portions. At this time, such a property is utilized that Si containing large amounts of an Si oxide (SiO2) and an impurity is at a lower etching rate as compared with Si containing a small amount of impurity. Consequently, only the piezoresistance element 3238 is left on the insulating film 3236 of SiO2. Thereafter a metal interconnection layer 3240 is selectively formed on the insulating film 3236, thereby completing the pressure sensor 3230.
The diaphragm 3224 is elastically deformed upon application of a pressure to be measured, whereby distortion following this elastic deformation changes electric resistance of the piezoresistance element 3238. The value of the pressure is measured through an amount of change of the electric resistance.
In this pressure sensor 3230, the piezoresistance element 3238 is formed on the insulating film 3236, to be electrically isolated from the substrate 3232. Therefore, no current flowing in the piezoresistance element 3238 leaks to the substrate 3232, whereby the amount of change of the electric resistance can be accurately measured.
 less than Micromachine Having Cantilever greater than 
FIG. 83 is a perspective view showing an acceleration sensor 3300 which is manufactured by a conventional method. In this acceleration sensor 3300, an SiO2 film 3304 is formed on a single-crystalline Si substrate 3302 having a groove 3308, while a cantilever 3306 forming a part of the SiO2 film 3304 protrudes above the groove 3308. Elastic deformation of the cantilever 3306 is detected by a distortion gauge, to measure the value of acceleration or vibration.
In order to manufacture this acceleration sensor 3300, an SiO2 film is formed on the overall surface of the substrate 3302 before formation of the groove 3308, whereafter the SiO2 film is selectively removed to be formed into the shape of the SiO2 3304 film having a protrusion. Then, the upper surface of the substrate 3302 is selectively etched to be provided with the groove 3308, while the protrusion of the SiO2 film 3304 defines the cantilever 3306.
(Problem of Prior Art 1)
However, the conventional micromachines which are manufactured in the aforementioned manners according to prior art 1 have the following problems:
First, the electrostatic motor 3000 (FIGS. 77 and 78) is so hardly worn that the same cannot withstand practical application to a motor, since both of the rotator 3008 and the rotary shaft 3014 which are in sliding contact with each other are made of polycrystalline Si. These members are made of polycrystalline Si since there is no technique of forming single-crystalline Si on the sacrifice layers 3006 and 3012 which are made of SiO2. In the actuator 3030 (FIG. 79), on the other hand, the level of elastic deformation of the movable parts 3036 is limited due to restriction in elastic limit and strength, since the movable parts 3036 are made of polycrystalline Si. The movable parts 3036 are made of not single-crystalline but polycrystalline Si since the same are formed by stacking Si on the sacrifice layers of SiO2.
In order to implement the complicated structure of the pressure sensor 3100 (FIG. 80) having the cavity 3106 storing the oscillator 3108 in its interior with single-crystalline Si, only the junction technique is generally employable since all members 3102, 3104 and 3108 are made of single-crystalline Si. Thus, the manufacturing steps are complicated since it is necessary to prepare the respective members independently of each other and high dimensional accuracy is required for the respective members to be joined to each other, while the members cannot be easily aligned with each other in junction.
Also in the pressure sensor 3200 (FIG. 81), it is necessary to previously prepare the two members 3202 and 3206 which are made of single-crystalline Si independently of each other for thereafter combining the same with each other by the junction technique, in order to implement the complicated structure provided with the groove 3204. Therefore, the manufacturing steps are complicated and difficult.
Also in the pressure sensor 3230 (FIG. 82), it is necessary to employ the aforementioned junction technique, in order to form the piezoresistance element 3238 of single-crystalline Si on the insulating film 3236 of SiO2. Therefore, the manufacturing steps are complicated and difficult, similarly to the above.
The acceleration sensor 3300 (FIG. 83) is insufficient in elastic limit, strength, uniformity of characteristics and the like since the cantilever 3306 is made of SiO2. In order to manufacture the acceleration sensor 3300 without employing the junction technique, it is necessary to selectively remove the substrate 3302 of single-crystalline Si while leaving the cantilever 3306 by etching. In general, therefore, the cantilever 3306 must be made of SiO2 or the like, dissimilarly to the substrate 3302.
(Prior Art 2)
FIGS. 99 to 102 illustrate steps of manufacturing a solar cell according to Prior Art 2. Description is now made with reference to an exemplary case of forming CdTe and CdS films, which are main materials for the solar cell, by printing, in addition to formation of electrodes. As shown in FIG. 99, a paste-type CdS film 3402 is first screen-printed on an upper surface of a glass substrate 3401. The CdS film 3402 is then dried by irradiation with infrared rays, and thereafter heated in a furnace to about 650xc2x0 C., to be converted to a sintered semiconductor. Then this CdS film 3402 is doped with an impurity to be converted to an n-type film. Then, a CdTe film 3403 is selectively screen-printed on a part of an upper surface of the CdS film 3402 as shown in FIG. 100, dried and sintered. Then, a carbon electrode 3404 (accepter source) is printed on an upper surface of the CdTe film 3403, dried and baked, as shown in FIG. 101. At this time, an element which is converted to an accepter at about 300xc2x0 C. is diffused in the CdTe film 3403 to form a strong p-type CdTe layer, thereby forming a p-n junction. Thereafter an Agxe2x80x94In electrode 3405 is printed/baked on an upwardly exposed portion of the CdS film 3402 while Ag electrodes 3406 are selectively printed/baked on parts of an upper surface of the carbon electrode 3404, as shown in FIG. 102.
While the solar cell shown in FIGS. 99 to 102 employs CdS belonging to the groups II and VI as an n-type film which is formed on a substrate, this film may alternatively be prepared from Si belonging to the group VI or GaAs belonging to the groups III and V, for example.
(Prior Art 3)
FIG. 103A illustrates a conventional solar cell of a tandem structure (stack system). Referring to FIG. 103A, numeral 3407 denotes a first semiconductor part (first heterojunction part), numeral 3408 denotes a second semiconductor part (second heterojunction part), and numeral 3409 denotes a tunnel junction part by high concentration junction. In general, a wavelength range of light which can be absorbed by a semiconductor is widened as a forbidden bandwidth Eg of the semiconductor is reduced, while the coefficient of energy use of the as-absorbed light is contradictorily deteriorated as the forbidden bandwidth is reduced. In the tandem structure, p-n junctions having different forbidden bandwidths Eg are overlappingly arranged in the direction of progress of the light along the order of the forbidden bandwidths Eg. As shown in FIG. 103B, the light is absorbed by the respective materials from a component of a shorter wavelength side, to develop voltages corresponding to EgA and EgB respectively. The semiconductor parts 3408 and 3409 having respective p-n junctions are connected in series, while excellent connection is attained through a tunnel current of the p+-n+ tunnel junction part 3409 with no interposition of a metal therebetween. Referring to FIG. 103B, symbol EC denotes a lower end of a conduction band, symbol EV denotes an upper end of a valence band, and symbol EF denotes a Fermi level, serving as a scale for expressing to which energy level electrons are filled in a solid. These energy gaps are naturally determined by the materials employed for the respective semiconductor films. The material for the tandem structure may be prepared from a combination of GaAlAs and GaAs, or a combination of a-Si and a-SiGe. A number of at least two is considered for the layers. Prior Art art 3 is also formed by a method of screen printing-drying-sintering in general, similarly to Prior Art 2.
(Problem of Prior Arts 2 and 3)
In each of the solar cells according to Prior Art 2 and Prior Art 3 shown in FIGS. 99 to 102, 103A and 103B, however, a single-crystalline thin film cannot be obtained since the solar cell is formed by the method of screen printing-drying-sintering, for example, and its crystal structure is generally amorphous. Thus, it is difficult to add a p-type or n-type impurity as well as to control the amount of introduction of the impurity, due to the heterogeneous crystal structure.
When a single-crystalline semiconductor substrate is employed as an underlayer, it is possible to form a single-crystalline film on an upper surface of the single-crystalline substrate serving as a seed crystal. However, the single-crystalline substrate itself is extremely high-priced, contrarily to requirement for reduction in cost. Further, a single-crystalline film must be formed under high-temperature environment in Prior Art 2 and Prior Art 3, and hence the substrate must be prepared from that which can withstand a high temperature, leading to increase in cost. Particularly when a plurality of semiconductor parts 3407 and 3408 having different forbidden bandwidths are stacked as in Prior Art 3, it is necessary to vary the materials therefor and hence preparation of a seed crystal from the underlayer itself is impossible.
When a semiconductor film is prepared from Si, for example, an absorption coefficient of crystalline Si is only 104/cm even in a visible part, and a considerably thick plate-type material is required for entirely absorbing sunlight, such that a thickness of several 100 xcexcm is required for a polycrystalline material. On the other hand, an amorphous material may have a relatively small thickness of about 1 xcexcm, for example, since the same has a large absorption coefficient. However, its conversion efficiency is deteriorated to about 5 to 10%, due to low electron mobility and a short carrier life time. To this end, GaAs is suitable as a material, while the same is not suitable in practice due to a high cost. A group II-VI or III-V compound is also preferable in consideration of an absorption coefficient and wavelengths of absorption ends and hence CdS, for example, has been temporarily studied. However, this material is hardly single-crystallized, and it is difficult to add a p-type or n-type impurity thereto. If the group II-VI or III-V compound can be single-crystallized and doped with an impurity, however, this compound is rather preferable as compared with Si. Thus, awaited is a method which can easily single-crystallize a group II-VI or III-V compound.
(Prior Arts 4 to 15)
FIG. 127 shows characteristics of materials for general solar cells. As shown in FIG. 127, the solar cells are classified into Si system and compound system ones, depending on the materials as employed. Most of the generally produced solar cells are prepared from Si-system materials. The Si-system materials include crystalline and amorphous materials. The crystallin materials are classified into single-crystalline Si and polycrystalline Si materials, depending on substrates as employed. Among the above, solar cells of the single-crystalline Si and polycrystalline Si materials are generally employed as power systems.
Although a solar cell employing single-crystalline Si has high conversion efficiency of 17% (to 20%), a single-crystalline Si substrate is disadvantageously high-priced.
On the other hand, a solar cell employing polycrystalline Si can be provided at a lower cost than the single-crystalline Si substrate, although its conversion efficiency of 12 to 14% is inferior to that of the single-crystalline Si solar cell. Also in such polycrystalline Si, however, a constant thickness or cutting allowance is required for a bulk substrate as employed so far as the bulk substrate is formed by cutting an ingot, leading to a high cost for the substrate.
An amorphous Si solar cell is expected in view of reduction in cost. The amorphous Si solar cell is manufactured by stacking thin films through a method such as plasma CVD (chemical vapor deposition). According to this method, the thin films can be formed at a low temperature of 200 to 300xc2x0 C., whereby a low-priced solar cell can be manufactured since a low-priced glass material or the like can be employed and the amount of the Si material can be extremely reduced as compared with a case of employing single-crystalline or polycrystalline bulk silicon. In order to put this solar cell into practice on a full scale, however, it is necessary to solve a problem of how to improve conversion efficiency, which is 6 to 8% under the present circumstances. Further, the amorphous Si is deteriorated by about 15% (initial deterioration) in several months by time change of the conversion efficiency due to a large amount of crystal defects, and thereafter further deteriorated by about 1 to 2% every year.
Description is now made on directions of research and development which are made by respective makers for solving the aforementioned problems of the prior art.
1) Single-Crystalline Si Solar Cell (Prior Art 4)
As shown in FIG. 128A, a polycrystalline base material 3501 is prepared by trichlorosilane which is lifted by the Czochralski method (CZ method), i.e., reduced with hydrogen with application of thermal energy, and single-crystallized with application of thermal energy of not more than 1500xc2x0 C. as shown in FIG. 128B to obtain a single-crystalline Si ingot 3502, which in turn is cut into a piece 3503 as shown in FIG. 128C and ground as shown in FIG. 128D, to obtain an Si single-crystalline substrate (wafer) 3504 with addition of a p-type impurity, as shown in FIG. 128E. When an n-type Si semiconductor layer 3505 shown in FIG. 129B is formed on an upper surface of an Si single-crystalline substrate (wafer) 3504 shown in FIG. 129A to form a p-n junction, on the other hand, employed is vapor phase diffusion employing PoCl3, application diffusion employing TiO2, SiO2 or P2O5, or ion implantation of directly doping the wafer with P+ ions. Then, a back electrode 3506 and front electrodes 3507 are formed as shown in FIG. 129C, to complete a single-crystalline Si solar cell. However, this method has such a problem that the cost is increased due to employment of large amounts of power and Si materials. Under the present circumstances, the point of the study resides in how to cut the substrate in a small thickness in cutting of the ingot 3502 shown in FIG. 128C and how to reduce loss (cutting allowance) of Si in such slicing, in addition to automation and continuation.
In a single-crystalline Si solar cell, conversion efficiency is improved to cover the high cost of a bulk silicon substrate. In order to prevent reduction of efficiency caused by carrier recombination in the vicinity of a back surface of a substrate, a BSF (back surface field) type solar cell is prepared by introducing an internal electric field into a back surface of a substrate 3504 as shown in FIG. 130A. A p+ layer 3508 is formed on the back surface of the p-type substrate 3504 to provide an internal electric field for accelerating carriers which are generated in the vicinity of the back surface by this electric field so that the same can be effectively extracted as power. Due to this structure, photosensitivity is increased particularly with respect to longer wavelengths, to improve conversion efficiency to about 15%.
FIG. 130B shows a violet cell, which is adapted to prevent reduction of efficiency caused by carrier recombination on a front side (photoreceiving side) of a solar cell. The thickness of an n+ layer 3505 of the solar cell, which is 0.3 to 0.5 xcexcm in general, is reduced by etching to 0.1 to 0.2 xcexcm, thereby preventing carrier recombination in the vicinity of the n+ layer 3505 and improving conversion efficiency.
FIG. 130C shows a CNR solar cell (Comsat non-reflective solar cell) for preventing reduction of efficiency caused by reflection of light on a surface of the solar cell. According to this solar cell, large amounts of fine pyramidal irregularities of 1 to 2 xcexcm are formed on surfaces of a substrate 3504 and an n+ layer 3505, to reduce surface reflection by multiple reflection. Due to this structure, conversion efficiency of 18%, which is at the maximum level in relation to an Si solar cell, is obtained. The thickness of the n+ layer 3505 is set at 0.2 to 0.3 xcexcm here.
FIG. 131 shows relation between a light passage distance and a ratio of light to incident light as to single-crystalline silicon which receives and absorbs sunlight (AM-O) in the exoatmosphere on the average revolution orbit of the earth. This relation shows that single-crystalline silicon of 30 xcexcm absorbs 80% of incident light, and 100 xcexcm is required for absorbing 90% of the incident light with the remaining 10%. Since contribution to absorption is thus reduced with separation from the surface, there is an idea of employing a silicon plate which is thin to some extent. FIG. 132 shows relation between substrate thicknesses of various solar cells and conversion efficiency levels as reached. Referring to FIG. 132, marks + show optimum points which can sufficiently satisfy maximum values in employment of the respective materials. This figure shows that an extremely small thickness of not more than 1 xcexcm is sufficient for amorphous Si (a-Si) having a large absorption coefficient. When a bulk single-crystalline Si substrate is employed, its conversion efficiency cannot exceed that of amorphous Si unless its thickness is in excess of 10 xcexcm, and a thickness of about 70 to 80 xcexcm is required at the optimum point. A solar cell formed with such a thickness can attain conversion efficiency which is close to 20%. Even if the thickness is increased in ekcess of 80 xcexcm, however, further improvement of the conversion efficiency cannot be expected in comparison with a single-crystalline Si substrate of about 70 to 80 xcexcm in thickness. In general, however, a single-crystalline substrate requires a wafer thickness of about 250 xcexcm and cutting allowance of about 150 xcexcm, and 25 wafers can be generally cut out from an ingot of 1 cm in length. While various cutting methods are studied, a total thickness of 300 xcexcm including a wafer thickness of 200 xcexcm and cutting allowance of 100 xcexcm is the current limit. Namely, it is impossible to produce the aforementioned wafer of 70 to 80 xcexcm in thickness, and it is necessary to employ a wafer of 200 to 400 xcexcm in thickness in practice. Thus, it is difficult to reduce the cost, due to loss of the material.
As to a silicon substrate which is applied to a solar cell, consideration is made on a way to provide a material at the minimum cost by preparing the material from low-purity substandard portions caused on upper and lower end portions of an ingot in a process of manufacturing a wafer for an LSI. However, substandard portions which are obtained from LSI wafer production with dependence of the substrate material on byproducts for LSI use are about 10%, and this leads to a problem of insufficiency in material if only the substandard portions are employed.
2) Polycrystalline Si Solar Cell
A single-crystalline Si solar cell is disadvantageous in such points that the manufacturing process therefor is complicated, manufacturing energy is at a high level and a large amount of Si materials are employed. In order to solve these problems, there have been developed cast methods shown in FIGS. 133 and 134 (Prior Arts 5 and 7), and a ribbon method shown in FIG. 135 (Prior Art 6) for manufacturing polycrystalline Si solar cells. As shown in FIG. 133, a general cast method (Prior Art 5) is adapted to cool (slowly cool) and solidify an Si solution 3511 in a crucible 3512. This method can attain higher productivity as compared with single-crystalline Si, while the as-obtained conversion efficiency is at a relatively high level of 10 to 16%, although this level is slightly inferior to that of single-crystalline Si. FIG. 134 shows a newly proposed cast method (Prior Art 7), which has been developed by New Energy and Industrial Technology Development Organization (NEDO) as a part of Japan Sun Shine Project. An Si solution 3511 which is contained in a crucible 3512 is slowly cooled with the crucible 3512 from above, to obtain a polycrystalline Si ingot of the same shape as the crucible 3512. Referring to FIG. 134, numeral 3531 denotes a heater, numeral 3514 denotes a heat shielding plate, numeral 3515 denotes a support shaft, and numeral 3516 denotes a chamber. A polycrystalline Si solar cell can be formed by slicing the ingot manufactured through the aforementioned step, through a step similar to that for single-crystalline Si.
The ribbon method is adapted to directly obtain a polycrystalline sheet 3521 which is required for a solar cell from an Si solution, as shown in FIG. 135. The raw material can be effectively utilized since there is no need to slice an ingot, dissimilarly to single crystal or cast method polycrystalline Si. In principle, ribbon polycrystalline Si is lifted through a capillary die 3523 which is uprightly provided in a crucible 3522 containing the Si solution. The as-lifted ribbon polycrystalline Si is cut into a proper size with a laser beam, to be worked into a solar cell through a step similar to that for single-crystalline Si. Conversion efficiency is 7 to 14%, which is slightly slower as compared with that obtained by the cast method.
The polycrystalline Si solar cell also has a problem in cost in a point that a large amount of Si raw material must be employed, similarly to the single-crystalline Si solar cell. A general technical problem in Prior Art 6 resides in xe2x80x9chow to cut a substrate in a small thickness and how to reduce loss in slicingxe2x80x9d, since the cost for a substrate material occupies about 25% of the cost for the overall solar cell in a high ratio.
In the cast method, the ingot is sliced with a multi-wire saw, to cause loss of about 120 to 150 xcexcm with respect to a substrate of 400 xcexcm. Namely, the Si raw material is used by 520 to 550 xcexcm, and the future technical subject resides in suppression of the same up to 300 xcexcm. Even if such reduction in thickness is implemented, however, the raw material is consumed about 10 to 100 times as compared with an amorphous Si solar cell as described below or the like.
3) Amorphous Si Solar Cell
An amorphous Si solar cell has excellent characteristics in cost, resource, manufacturing energy and environmental pollution, although the same is still disadvantageous in conversion efficiency and reliability.
The amorphous Si solar cell is manufactured by a method which is absolutely different from that for a solar cell employing a crystalline bulk Si substrate. FIGS. 136 and 137 schematically show a single-chamber reaction furnace method (Prior Art 8) and a continuous separation plasma reaction method (Prior Art 9) respectively. In either method, a raw material gas 3526 such as monosilane (SiH4) is introduced into a reaction chamber 3524 which is maintained in a vacuum of 0.1 to 10 Torr, and an RF electric field 3525 is applied to decompose the raw material gas 3526, thereby forming an amorphous Si layer 3528 on a substrate 3527 of glass or stainless steel. At this time, p-type amorphous Si or n-type amorphous Si is formed when B2H6 (diborane) 3529 or phosphine (PH3) 3530 is mixed into the raw material gas 3526. Referring to FIG. 137, numeral 3531 denotes a shutter. Thus, a p-n junction can be formed by simply switching the raw material gas 3526. The amorphous Si solar cell requires small manufacturing energy, and the Si layer forming an element is reduced to {fraction (1/100)} as compared with single-crystalline and polycrystalline bulk silicon solar cells, to implement reduction in cost. Further, the film formation temperature is so reduced that a low-priced substrate of glass or stainless steel can be employed, to also effectively reduce the cost.
The amorphous Si solar cell is different in principle of power generation and structure from a crystalline Si solar cell. In general, crystalline silicon has a p-n structure as shown in FIG. 138, and photocarriers are moved by diffusion. On the other hand, the amorphous Si solar cell has a p-i-n (p-type-intrinsic-n-type) structure which is prepared by interposing an intrinsic semiconductor layer (i) between a p-type layer (p) and an n-type layer (n) as shown in FIG. 139, and photocarriers are mainly moved by drifting by an electric field contained in the solar cell. Referring to FIG. 139, TCO denotes a transparent conductive oxide film which serves as an electrode, and Gs denotes a glass plate. Due to such provision of the intrinsic semiconductor layer (i), most of electrons and holes are generated by light in a portion having the internal electric field, i.e., a depletion layer, since a space-charge region (depletion layer) in a boundary of an ordinary p-n junction is wide and hence the electrons and holes can be immediately extracted as a photogenerated current. Namely, it is possible to omit a process of movement of minority carriers to a p-n boundary region by diffusion in an ordinary p-n junction. In this case, however, part of incident light is absorbed by a p-type doped layer before reaching the intrinsic semiconductor layer (i) and not effectively utilized for power generation since amorphous Si has a large absorption coefficient while photocarriers are generated mainly in the intrinsic semiconductor layer (i) in the amorphous Si solar cell. FIG. 140 shows comparison of light absorption coefficients with respect to wavelengths (energy of photons) of light in relation to amorphous Si and crystal silicon etc., and FIG. 141 shows comparison of light absorption spectra of amorphous Si:H mixed with hydrogen and single-crystalline Si. It is understood from FIGS. 140 and 141 that the amorphous Si or the amorphous Si:H has a larger absorption coefficient by about 1 digit as compared with the single-crystalline Si in the vicinity of 0.5 xcexcm forming the peak of solar energy. It is also understood that the single-crystalline Si has a larger coefficient absorption by one digit than the amorphous Si on a longer wavelength side beyond the wavelength of 0.7 xcexcm.
FIG. 142 shows light absorption states with parameters of light absorption coefficients, by plotting rates of absorption of photons with respect to distances of light passage while setting values of absorption coefficients. FIG. 142 shows four curves with light absorption coefficients of 102, 103, 104 and 105. It is understood that the amorphous Si can be reduced in thickness as compared with the single-crystalline silicon and is suitable for a thin film structure since a large quantity of light is absorbed in a short distance when the light absorption coefficient is at a high level.
The above description is summarized as follows:
1. An extremely thin layer is sufficient for an amorphous Si type, which has a large absorption coefficient. However, its conversion efficiency is maximum at 14% in theory as shown in FIG. 132, and is extremely low as compared with the conversion efficiency of single-crystalline Si exceeding 20%.
2. While photocarriers are mainly generated in the intrinsic semiconductor layer (i) shown in FIG. 139 in the amorphous Si type, part of incident light is absorbed by the p-type doped layer before reaching the intrinsic semiconductor layer (i), and is not effectively used for power generation. It is important to polycrystallize or single-crystallize the doped layer in order to reduce the doped layer on the incident light side and increase the quantity of light reaching the intrinsic semiconductor layer (i), while it is difficult to attain this. While it is necessary to reduce a process temperature particularly when a low-priced glass substrate or the like is employed, it is difficult to implement this by a conventional method since Si has a high crystallization temperature.
3. In a solar cell employing amorphous Si, remarkable improvement of conversion efficiency can be expected if it is possible to arrange a cell having sensitivity to shorter wavelengths on a light input side (front side) and to arrange a cell having sensitivity to longer wavelengths on a back side, since the wide wavelength range of the sunlight can be effectively utilized. To this end, conversion efficiency is improved if it is possible to arrange amorphous Si on a front cell and to arrange a single-crystalline or polycrystalline silicon thin film on a back side. In order to implement such a structure in the prior art, however, it is necessary to employ a bulk silicon single-crystalline substrate. Thus, a low-priced glass substrate or the like cannot be employed and the substrate is increased in thickness, to sacrifice cost reduction.
4. In a cell having excellent absorption with a large absorption coefficient, it is necessary to effectively extract minority carriers among electrons and holes generated by light in the vicinity of the surface, i.e., electrons in a p-type semiconductor or holes in an n-type semiconductor. To this end, it is important to reduce crystal defects or to reduce the depth of a p-type layer so that the as-generated minority carriers can be effectively moved to a depletion layer to be extracted, since a large amount of crystalline defects are inevitably caused in a doped layer (p-type layer in a p-i-n structure) having high concentration of an impurity in the surface part such that electrons and holes are immediately recombined and annihilated. Although a general amorphous Si film contains hydrogen which is coupled with uncoupled ones to reduce defects, defect density is higher by 3 to 5 digits than single-crystalline Si to cause significant loss by surface recombination. Amorphous Si has defect density of 1020/cm3, amorphous Si (amorphous Si:H) hydrogenated by glow discharge (plasma CVD) has defect density of 1015 to 1017/cm3, and single-crystalline Si has defect density of 1012/cm3.
FIG. 143 shows physical constants of amorphous Si:H and single-crystalline Si. As understood from FIG. 143, electric characteristics of the amorphous Si:H such as mobility of electrons and holes, diffusion length, life times of electrons and holes and the like are inferior to those of single-crystalline silicon, leading to inferior conversion efficiency.
Thus, it is preferable to arrange a crystalline silicon thin film layer on a front side, to form an intrinsic semiconductor layer by an amorphous Si thin film and to arrange a crystalline silicon thin film having an excellent absorption coefficient for a longer wavelength side on a back side, in order to manufacture a solar cell having a smaller amount of silicon material (reduction in thickness) and excellent conversion efficiency by effectively utilizing optical and electric characteristics. In general, however, it is difficult to form a single-crystalline or polycrystalline silicon thin film on an amorphous Si thin film since a single-crystalline or polycrystalline thin film cannot be formed on a low-priced glass substrate and single-crystalline Si can be formed only on a single-crystalline substrate in general.
FIGS. 144 to 147 show exemplary proposals (Prior Arts 10 to 13) in relation to a solar cell of amorphous silicon carbide (amorphous SiC) having sensitivity to short-wave light, which is arranged on a front side on a base of an amorphous Si layer or the like. Referring to each of FIGS. 144 to 147, numeral 3535 denotes a glass substrate, numeral 3536 denotes a transparent conductive oxide (TCO) film, numeral 3537 denotes a p-type amorphous SiC film, numeral 3538 denotes an intrinsic amorphous Si layer, numeral 3539 denotes an n-type amorphous Si film, and numeral 3541 denotes a back-side electrode of aluminum or silver. Referring to FIG. 145, numeral 3542 denotes an n-type microcrystal Si layer, numeral 3543 denotes a TiO2 layer and numeral 3544 denotes a semi-texture structure (SuS) layer, while numeral 3545 in FIG. 146 denotes a graded hand-gap amorphous SiC layer, and numeral 3546 in FIG. 147 denotes a highly qualified intrinsic amorphous Si layer. As shown in FIG. 148, performed is improvement/research of arranging an intrinsic amorphous SiGe layer 3547 on a back side (Prior Art 14). However, the absorption coefficient is lowered in relation to longer wavelengths as shown in FIG. 141 since all these layers are prepared from amorphous materials. Thus, this technique is not yet put into practice due to problems of electric characteristics in relation to covering of a wide frequency band. While a polycrystalline Si layer 3548 is arranged on a back end in Prior Art 15 as shown in FIG. 149, the material for the substrate is restricted to a high-priced one in this case since the substrate material must withstand high-temperature environment for crystallizing the polycrystalline Si film 3548.
(Problem of Prior Arts 4 to 15)
The aforementioned problems of Prior Arts 4 to 15 are summarized as follows:
1) A crystalline Si solar cell (Prior Arts 4 to 7) requires a substrate thickness of 200 xcexcm at the minimum and 300 xcexcm in general, since a bulk silicon wafer must be employed. Further, the silicon wafer is cut out from an ingot and hence cutting loss of 120 to 150 xcexcm is caused leading to requirement for an Si material of 320 to 450 xcexcm in thickness as a whole.
In order to attain conversion efficiency of 20% which is close to the theoretical value, loss of the material is caused since the crystalline Si film may have a thickness of 70 to 80 xcexcm, leading to increase in cost.
It is necessary to reduce the thickness of the silicon wafer to minimize loss in cutting in order to reduce the cost, while it is difficult to reduce the thickness below 200 xcexcm in view of the yield, and it is also difficult to reduce the loss in cutting below 100 xcexcm, so far as a multi-wire saw or the like is employed. Thus, cost reduction for the solar cell is limited.
2) In the crystalline Si substrate (Prior Arts 4 to 7), which is mainly prepared by a method of utilizing substandard portions on upper and lower ends of an ingot for an LSI for reducing the cost, the resource therefor tends to be insufficient in general.
3) In the amorphous Si solar cell (Prior Arts 8 to 15), cost reduction can be implemented since the light absorption coefficient in the vicinity of the peak (500 xc3x85) of solar energy is higher by at least one digit as compared with a single-crystalline Si solar cell and hence a larger quantity of light is absorbed in a short distance and the film thickness can be reduced to not more than {fraction (1/100)} as compared with the single-crystalline solar cell. Further, the amorphous Si is effective for cost reduction since the film forming temperature is at a low level and a low-priced glass substrate can be employed. However, the same has a large amount of crystal defects which is larger by 3 to 5 digits as compared with the single-crystalline Si solar cell, while electrons and holes are easily annihilated by recombination, mobility is lower by 4 to 5 digits leading to inferior conversion efficiency, and the same is easily deteriorated by time change.
(Prior Art 16)
Conventional semiconductor devices (semiconductor memory devices) for serving as mass storage devices include a volatile dynamic random access memory (hereinafter referred to as a DRAM) and an electrically writable/erasable nonvolatile memory such as a flash EPROM.
FIG. 207 is a sectional view showing a semiconductor device for serving as a DRAM according to Prior Art 16, and FIG. 208 illustrates an internal circuit of a ferroelectric memory device employing ferroelectric substances for capacitor parts by Ramtron Corp., for example. Referring to FIGS. 207 and 208, numeral 3601 denotes a p-type semiconductor substrate, numeral 3602 denotes a transistor part, numeral 3603 denotes a bit line, numeral 3604 denotes a LOCOS oxide film, numeral 3605 denotes a polycrystalline (polysilicon/polycide) word line, numeral 3606 denotes a first insulating film, numeral 3607 denotes a capacitance part (data holding part), numeral 3608 denotes a first wire connecting the transistor part 3602 with the capacitance part 3607, numeral 3609 denotes a dielectric film, numeral 3610 denotes an upper electrode of the capacitance part 3607, and numeral 3611 denotes a plate.
In the conventional memory device employing ferroelectric substances for capacitors, a 1-bit memory cell is formed by two transistors and two capacitors as shown in FIG. 208 due to remarkable dispersion in charge quantity caused by the dielectric constant and polarization of the capacitance part 3607, and the capacitors are polarized in opposite directions to guarantee data by detecting the difference therebetween.
In general, the dielectric film 3609 of the capacitance part 3607 is formed by a ferroelectric film. In such a ferroelectric film, dielectric constants of crystals are increased with temperature reduction to cause phase transition by divergence at a certain critical temperature (Curie temperature) thereby causing spontaneous dielectric polarization in a low-temperature phase. Such a ferroelectric film is prepared from PZT consisting of mixed crystals of PbZrO3 and PbTiO3 or BST consisting of mixed crystals of BaTiO3 and SrTiO3. While such a material is in a perovskite or pyrochlore structure, it is necessary to utilize a perovskite crystal system since a pyrochlore crystal system has a low dielectric constant. In general, the aforementioned ferroelectric film is generally formed by a polycrystalline thin film.
(Prior Art 17)
FIG. 209 is a sectional view showing a semiconductor device for serving as a nonvolatile memory device (EPROM/flash EPROM) according to Prior Art 17. Referring to FIG. 209, numeral 3621 denotes a p-type semiconductor substrate, numeral 3622 denotes a LOCOS oxide layer (SiO2), numeral 3623 denotes a gate insulating film, numeral 3624 denotes a floating gate, numeral 3625 denotes a control gate, and numeral 3626 denotes an interlayer insulating film which is interposed between the gates 3624 and 3625. The floating gate 3624 is prepared from polycrystalline silicon (polysilicon). The interlayer insulating film 3626 is formed by a multilayer film (oxi-nitride: ONO) consisting of silicon oxide (SiO2) and silicon nitride (SiN) or independently prepared from silicon oxide (SiO2), so that an SiO2 layer is in contact with the floating gate 3624 in either case. In formation of this interlayer insulating film 3626, the polysilicon forming the floating gate 3624 is oxidized to grow SiO2.
(Prior Art 18)
FIG. 210 is a sectional view showing a semiconductor device for serving as a nonvolatile memory device (EPROM/flash EPROM) according to Prior Art 18. Referring to FIG. 210, members having the same functions as those in Prior Art 17 are denoted by similar reference numerals. In the semiconductor device according to Prior Art 18 which aims at a higher degree of integration as compared with that according to Prior Art 17, a source 3627 and a drain 3628 are formed by embedding/diffusion to form a transistor. Also in the semiconductor device according to Prior Art 18, a floating gate 3624 is prepared from polycrystalline silicon (polysilicon) and an interlayer insulating film 3626 is formed by a multilayer film (ONO) consisting of silicon oxide (SiO2) and silicon nitride (SiN) or independently prepared from silicon oxide (SiO2), so that an SiO2 layer is in contact with the floating gate 3624 in either case. In formation of this interlayer insulating film 3626, the polysilicon forming the floating gate 3624 is oxidized to grow SiO2, similarly to Prior Art 17.
(Prior Art 19)
FIG. 212 is a circuit diagram of a memory cell forming a memory array of a general DRAM according to Prior Art 19. Referring to FIG. 212, symbol 3632 denotes a transistor part, symbol 3633 denotes a bit line, symbol 3635 denotes a word line, and symbol 3637 denotes a capacitance part (data holding part). According to Prior Art 19, a 1-bit memory cell can be formed by a single transistor part and a single capacitance part, whereby it is possible to attain relatively large capacitance.
In such a DRAM which is a volatile memory device, however, information as stored is lost when power is removed. Therefore, it is necessary to regularly supply power in order to hold the stored information, and the application range of this DRAM is disadvantageously limited.
(Prior Art 20)
FIG. 213 is a sectional view showing a memory cell (memory transistor) of a general flash EPROM according to Prior Art 20. Referring to FIG. 213, symbol 3641 denotes a semiconductor substrate, symbol 3642 denotes a floating gate which is formed above the semiconductor substrate 3641, symbol 3643 denotes a control gate which is formed above the floating gate 3642, and symbols 3644 and 3645 denote a source diffusion region and a drain diffusion region which are selectively formed on an upper surface of the semiconductor substrate 3641. A thin gate insulating film (oxide film) is formed in a clearance 3646 between the floating gate 3642 and the semiconductor substrate 3641 for moving electrons through a tunnel phenomenon.
Operation of the flash EPROM is now described. First, the source diffusion region 3644 is grounded and a program voltage is applied to the drain diffusion region 3645 while a voltage is applied to the control gate 3643, whereby the memory cell enters an ON state to allow a current flow. At this time, avalanche breakdown takes place in the vicinity of the drain diffusion region 3645, to generate electron-hole pairs. The holes flow to the ground potential through the semiconductor substrate 3641, while the electrons flow toward a channel 3629 direction into the source diffusion region 3644. However, parts of the electrons are accelerated by an electric field which is developed across the floating gate 3642 and the drain diffusion region 3645, to be injected into the floating gate 3642. Consequently, the threshold voltage of the memory cell is increased. In this state, information xe2x80x9c0xe2x80x9d is stored. In order to erase the information, on the other hand, the drain diffusion region 3645 is opened, the control gate 3643 is grounded and a voltage is applied to the source diffusion region 3644. Then, a tunnel phenomenon is caused by an electric field which is developed across the source diffusion region 3644 and the floating gate 3642, to extract the electrons from the floating gate 3642. Consequently, the threshold voltage of the memory cell is reduced. In this state, information xe2x80x9c1xe2x80x9d is stored.
Such a flash EPROM can be regarded as having a higher possibility for mass storage than a DRAM since a 1-bit memory cell can be formed by a single memory transistor. However, this device has a problem of a slow data writing/erasing time. Further, a high electric field is applied to the memory transistor in data writing/erasing to inject or extract electrons through the gate insulating film which is formed in the clearance 3646. Thus, the gate insulating film provided in the clearance 3646 is fatigued with data writing and erasing operations to be gradually reduced in remanence and finally broken. Thus, the number of writing/erasing times is limited.
(Prior Art 21)
In order to solve the aforementioned problems of Prior Art 16 and Prior Art 20, Ramtron Corp. has developed a nonvolatile DRAM (hereinafter referred to as an FRAM) in which a dielectric film of a capacitance part is made of a ferroelectric substance (refer to Nikkei Microdevices, June 1992, pp. 78 to 83 and Japanese Patent Laying-Open Gazettes Nos. 64-66897 (1989), 64-66899 (1989), 1-278063 (1989) and 2-113496 (1990)).
FIG. 214 is a sectional view showing an exemplary ferroelectric DRAM according to Prior Art 21, in which a capacitor part (capacitance part) is made of a ferroelectric substance. An internal circuit of this semiconductor memory device is similar to that of Prior Art 16 shown in FIG. 208, and members having the same functions as those shown in FIG. 208 are denoted by the same reference numerals in the following description. Referring to FIGS. 208 and 214, numeral 3601 denotes a p-type semiconductor substrate, numeral 3602 denotes a transistor part, numeral 3603 denotes a bit line, numeral 3604 denotes a LOCOS oxide film, numeral 3605 denotes a polycrystalline (polysilicon/polycide) word line, numeral 3606 denotes a first insulating film, numeral 3607 denotes a capacitance part (data holding part), numeral 3608 denotes a first wire connecting the transistor part 3602 with the capacitance part 3607, numeral 3609 denotes a dielectric film which is made of a ferroelectric substance, numeral 3610 denotes an upper electrode of the capacitance part 3607, and numeral 3611 denotes a plate.
In the memory device according to Prior Art 21 employing a ferroelectric substance for a capacitor, a 1-bit memory cell is formed by two transistors and two capacitors as shown in FIG. 208 due to remarkable dispersion in charge quantity caused by the dielectric constant and polarization of the capacitance part 3607, and the capacitors are polarized in opposite directions to guarantee data by detecting the difference therebetween.
In such a ferroelectric film which is employed for forming the dielectric film 3609 of the capacitance part 3607, dielectric constants of crystals are increased with temperature reduction to cause phase transition by divergence at a certain critical temperature (Curie temperature) thereby causing spontaneous dielectric polarization in a low-temperature phase. Such a ferroelectric film is prepared from PZT consisting of mixed crystals of PbZrO3 and PbTiO3 or BST consisting of mixed crystals of BaTiO3 and SrTiO3. While such a material is in a perovskite or pyrochlore structure, it is necessary to utilize a perovskite crystal system since a pyrochlore crystal system has a low dielectric constant. In order to implement such a ferroelectric substance having a perovskite crystal structure, an electrode of the ferroelectric substance is generally in a multilayer film structure in which a Pt layer is arranged in an interface with the ferroelectric substance, so that no electrode material (particularly a metal material) enters crystals of the ferroelectric substance to cause a leakage current or deterioration of film characteristics, thereby attaining excellent crystallinity of the ferroelectric substance. In Prior Art 21, the aforementioned ferroelectric film is generally prepared from an amorphous film.
(Prior Art 22)
FIG. 215 illustrates a semiconductor device for serving as a nonvolatile memory device (EPROM/flash EPROM) according to Prior Art 22. As shown in FIG. 215, the semiconductor device according to Prior Art 21 is a ferroelectric gate field effect transistor (hereinafter referred to as MFSFET) in which a memory cell is formed by a transistor 3652 having a gate insulating film 3651 of a ferroelectric substance (refer to Japanese Patent Laying-Open Gazette No. 4-192173 (1992), for example). Referring to FIG. 215, symbol 3653 denotes a p-type semiconductor substrate, symbol 3654 denotes a gate electrode, symbol 3655 denotes a source and symbol 3656 denotes a drain.
Also in the semiconductor device according to Prior Art 22, the ferroelectric film is prepared from PZT consisting of mixed crystals of PbZrO3 and PbTiO3 or BST consisting of mixed crystals of BaTiO3 and SrTiO3. Further, the ferroelectric film is generally prepared from an amorphous film also in the semiconductor device according to Prior Art 22.
(Problem of Prior Art 16)
When the ferroelectric film 3609 for the capacitance part 3607 is formed by a polycrystalline or amorphous thin film in Prior Art 16, a polarization field curve (PE hysteresis curve) with respect to an external electric field is rhomboidally dulled as shown in FIG. 211, to cause dispersion such that remanence is reduced and the dielectric constant is also reduced.
Further, a metal forming the electrode may enter between crystal grains of the ferroelectric film 3609, to cause a leakage current or deterioration in durability. Although there has been proposed a method of depositing a thin RuO2 film on the electrode or adding about several to 10% of La to PZT in order to solve this problem, the dielectric constant is reduced by about 1 digit in either case. While PZT is held by multilayer metals including a Pt layer to be improved in crystallinity in the ferroelectric memory device by Ramtron Corp., for example, the fabrication cost is increased in this case. Thus, none of the aforementioned methods is sufficiently practicable.
As a material for the dielectric film 3609 for the capacitance part 3607 of the conventional DRAM, SiO2, Sixe2x80x94N, Ta2O5 or the like has been put into practice or studied. The capacitance part generally requires storage capacitance of about 20 to 40 fF, which remains substantially unchanged upon refinement of the device. In a mass storage DRAM, therefore, a capacitive surface area is increased by a complicated structure such as a stack, trench or fin type structure to suppress the cell size. When such a complicated capacitance structure is implemented, however, the number of fabricating steps is inevitably increased. In recent years, therefore, study has been developed to apply a polycrystalline dielectric film having a high dielectric constant to the dielectric film 3609 of the capacitance part 3607. In this case, it is necessary to regulate the crystalline structure in order to suppress dispersion in dielectric constant thereby stabilizing characteristics, while such stabilization of characteristics is limited in a polycrystalline or amorphous thin film. A film thickness of at least 2000 xc3x85 is required in order to obtain a stable film, while the area of the capacitance part 3607 must also be increased in this case and hence it is impossible to cope with refinement of the device.
(Problems of Prior Art 17 and Prior Art 18)
For example, a flash EPROM has a high data reading speed of about several 10 to 200 nsec. in general, while a data writing or erasing operation requires an extremely long time of several xcexcsec. to several msec. depending on the system, and there has been strong requirement for increase in speed. In the semiconductor device having a two-layer structure provided with a floating gate according to each of Prior Art 17 and Prior Art 18, it is necessary to increase a coupling coefficient (GCR) in order to improve writing efficiency etc.
Assuming that C1 represents capacitance between the floating gate 3624 and the semiconductor substrate 3621 and C2 represents that between the floating gate 3624 and the control gate 3625, the coupling coefficient (GCR) is in proportion to C2/(C1+C2). Namely, it is effective to maximize the capacitance C2 between the floating gate 3624 and the control gate 3625. This can be attained by the following three methods:
(1) To reduce the thickness of the interlayer insulating film 3626 which is provided between the gates 3624 and 3625.
(2) To increase the dielectric constant of the interlayer insulating film 3626.
(3) To increase the overlap area of the gates 3624 and 3625.
In practice, however, the device has the following restrictions:
[1] The thickness of the interlayer insulating film 3626 is decided due to requirement in performance for ensuring withstand voltages of about 30 to 40 V for the floating gate 3624 and the control gate 3625. Namely, the thickness must be maintained at a certain degree since the interlayer withstand voltage is disadvantageously reduced if the thickness is reduced. In more concrete terms, the gate insulating film 3623 has a thickness (distance between the floating gate 3624 and the semiconductor substrate 21) of about 20 nm and the interlayer insulating film 3626 has a thickness (distance between the floating gate 3624 and the control gate 25) of about 60 nm (SiO2: 10 nm and SiN: 50 nm in ONO structure) in a general EPROM.
[2] The material for the interlayer insulating film 3626 is restricted to an ONO or SiO2 film, and hence it is impossible to increase the dielectric constant of the interlayer insulating film 3626 so far as such a material is employed. In more concrete terms, SiO2 and ONO films have dielectric constants of about 3.9 and 6 to 9 respectively. It may conceivably be possible to employ a film of BST consisting of mixed crystals of BaTiO3 and SrTiO3) or PLZT obtained by adding La to mixed crystals of PbZrO3 and PbTiO3 as a high dielectric film. This material has a dielectric constant of about 300, which is higher by 30 to 50 times than that of the ONO film. In a conventional fabrication method, however, a thickness of at least 200 nm (300 to 400 nm in practice) is required in order to stabilize the properties of the film, and hence it is necessary to hold the film with multilayer metals including a Pt layer or the like in order to improve crystallinity of the film. Thus, this film is unsuitable for the interlayer insulating film 3626 provided between the gates 3624 and 3625 of the memory device, and is not put into practice.
[3] In each of Prior Art 17 and Prior Art 18, the area S1 of the floating gate 3624 is substantially doubled as compared with the area S2 of the channel region so that the capacitance C2 between the floating gate 3624 and the control gate 3625 is larger than the capacitance C1, in order to attain a coupling coefficient of about 0.6. While the capacitance C2 is increased when the overlap area between the floating gate 3624 and the control gate 3625 is thus increased, however, the memory cell area is inevitably increased contrarily to the requirement for miniaturization of the device. In order to attain a coupling coefficient (GCR) of 0.6 to 0.7, the overlap area between the floating gate 3624 and the control gate 3625 is doubled or tripled as compared with the area of the channel region. While it is necessary to reduce the overlap area between the floating gate 3624 and the control gate 3625 in order to reduce the memory cell area, the coupling coefficient cannot be reduced below 0.5, in order to maintain performance of the memory device. In particular, it is possible to reduce the cell area by separating adjacent cells from each other by a trench T (see FIG. 172). In this case, however, the area S1 of the floating gate 3624 must be substantially equalized to the area S2 of the channel region in design, and the coupling coefficient is deteriorated to about 0.4 in this case. Particularly when the semiconductor device according to Prior Art 18 is formed not by embedding/diffusion but N+ injection with a mask of the floating gate 3624 in self alignment, the size of the floating gate 3624 is inevitably equalized to that of the channel region. In this case, the coupling coefficient is extremely reduced.
In each of Prior Art 17 and Prior Art 18, further, the floating gate 3624 is made of polysilicon and grown by oxidation to form the interlayer insulating film 3626, and hence these layers are inferior in crystallinity and not dense in film quality.
Further, it is difficult to form the floating gate 3624 in a flat state due to the polycrystalline structure of its surface, and the floating gate 3624 is generally provided with projections. When the floating gate 3624 is oxidized in this state, the projections are further grown due to a high oxidation speed. These projections extremely reduce the withstand voltage of the interlayer insulating film 3626 provided between the floating gate 3624 and the control gate 3625. Therefore, it is necessary to smooth such projections before oxidation of the floating gate 3624 by implanting Ar+ or As+ into the polysilicon at about 50 keV and bringing the polysilicon surface of the floating gate 3624 into an amorphous state. Thus, the processing steps are increased to increase the fabrication time.
(Problem of Prior Art 19)
In the DRAM according to Prior Art 19 which is a volatile memory device, information as stored is lost when power is removed as hereinabove described. Therefore, it is necessary to regularly supply power in order to hold the stored information, and the application range of this DRAM is limited.
While a 1-bit memory cell is formed by a single transistor part and a single capacitance part in the semiconductor device according to Prior Art 19, a concrete system for forming a 1-bit memory cell by only a single transistor part is desired in order to further miniaturize the memory cell.
(Problem of Prior Art 20)
In the semiconductor device according to Prior Art 20, the data writing/erasing is at a slow speed and the gate insulating film provided in the clearance 3646 is fatigued with data writing and erasing operations to be finally broken, as hereinabove described. Thus, the number of writing/erasing times is limited.
(Problem of Prior Art 21)
In the semiconductor device according to Prior Art 21, a 1-bit memory cell is formed by two transistors and two capacitors as shown in FIG. 208, and hence miniaturization of the memory cell is limited. Thus, a concrete system for forming a 1-bit memory cell by only a single transistor part is desired, as hereinabove described.
Further, a multilayer film forming step is complicated in the semiconductor device according to Prior Art 21 due to the multilayer film structure including a Pt layer, and hence simplification of the steps in mass production is limited.
(Problem of Prior Art 22)
Although a 1-bit memory cell is formed by a single transistor in the MFSFET according to Prior Art 22, internal crystallinity is inferior due to an amorphous film which is applied to the gate insulating film 3651 of a ferroelectric substance in particular, and hence its film thickness must be increased to some extent. In order to ensure a constant breakdown voltage for the gate insulating film 3651, therefore, a single transistor memory cell is increased in area. Thus, it is impossible to implement a practical degree of integration when a plurality of cells are arranged in parallel with each other.
In order to implement the MFSFET according to Prior Art 22, it is necessary to form a perovskite crystalline film of a ferroelectric substance on an upper surface of a silicon film (Si), a silicon oxide film (SiO2) or a silicon nitride film (Sixe2x80x94N) as an underlayer. Under the present circumstances, however, there has been announced no effective method of crystallizing a perovskite film of a ferroelectric substance, and it is extremely difficult to single-crystallize the same in particular. Therefore, improvement of polarization field characteristics of the ferroelectric substance with respect to an external electric field is limited. Particularly in formation of a thin film, a problem is caused in stability of characteristics.
(Prior Art 23)
FIG. 231 illustrates a general 6-transistor CMOS-SRAM cell. The SRAM is formed by nMOS transistors N1 and N2, a CMOS flip-flop in which an input and an output of a CMOS inverter pair connected with single ones of pMOS transistors P1 and P2 respectively are cross-connected with each other, and nMOS transfer transistors N3 and N4. When information is xe2x80x9c1xe2x80x9d, the transistors P1 and N2 conduct while the transistors P2 and N1 enter nonconducting states. When information is xe2x80x9c0xe2x80x9d, on the other hand, the transistors P1 and N2 enter nonconducting states while the transistors P2 and N1 conduct. Consequently, no consumption current flows in this cell in a standby state except a leakage current component, whereby power consumption can be saved in the standby state.
FIG. 232 is a sectional view showing a semiconductor device according to prior art 23, in which the pMOS transistor P1 provided in the SRAM shown in FIG. 231 is formed by a TFT. Referring to FIG. 232, numeral 3701 denotes a substrate, numeral 3702 denotes a wire to be connected to a gate of the nMOS transistor N1, numeral 3703 denotes a first insulating film, numeral 3704 denotes a gate of the pMOS transistor P1, numeral 3705 denotes a wire to be connected to gates of the pMOS transistor P2 and the nMOS transistor N2, numeral 3706 denotes a second insulating film, numeral 3707 denotes a drain of the transistor P1, numeral 3708 denotes a source of the transistor P1, and numeral 3709 denotes a channel interposed between the drain 3707 and the source 3708.
In the prior art 23, the wires 3702 and 3705, the gate 3704, the drain 3707, the source 3708 and the channel 3709 are formed by polycrystalline (polysilicon) or amorphous silicon films.
(Prior Art 24)
FIG. 233 is a sectional view showing a semiconductor device according to prior art 24, in which a TFT is built into a display device of an active matrix liquid display. Referring to FIG. 233, numeral 3711 denotes a condensed capacitance part, numeral 3712 denotes a TFT, numeral 3713 denotes a glass substrate, numeral 3714 denotes a lower electrode of aluminum or the like for the condensed capacitance part 3711, numeral 3715 denotes an Al2O3 film, numeral 3716 denotes a transparent upper electrode (ITO) for the condensed capacitance part 3711, numeral 3717 denotes a gate of MoTa or the like for the TFT 3712, numeral 3718 denotes an Si channel for the TFT 3712, numeral 3719 denotes a source of n+-type Si or the like for the TFT 3712, numeral 3721 denotes a drain of n+-type Si or the like for the TFT 3712, and numeral 3722 denotes a dielectric film (gate insulating film) of SiNx or SiO2. FIG. 234 is an enlarged sectional view showing the TFT 3712. Referring to FIG. 234, numeral 3723 denotes an SiNx film for serving as a gate insulating film, numeral 3724 denotes an amorphous Si film, and numeral 3725 denotes an electrode of Mo/Al or the like. Referring to FIG. 234, the TFT 3712 is generally formed in order of the gate 3717, the gate insulating films 3722 and 3723, the amorphous Si film 3724, the Si channel 3718, the source 3719 and the drain 3721, and the electrode 3725. The gate insulating films 3722 and 3723, the lower electrode 3714 for the condensed capacitance part 3711, the gate 3717 and the Si channel 3718 are in polycrystalline or amorphous structures.
(Problem of Prior Art 23)
While the drain 3707, the source 3708 and the channel 3709 of the TFT according to the prior art 23 are formed by polycrystalline (polysilicon) or amorphous silicon films, the ratio of a drain current in an ON state of the transistor to that in an OFF state is small in a TFT employing polysilicon, for example. When an OFF-state current is reduced in order to reduce a standby current of the SRAM in this case, the ON-state current is also reduced such that it takes time to charge the potential of the memory cell immediately after writing from Vccxe2x88x92Vth to Vcc, and hence the access time is retarded. When the ON-state current is increased, on the other hand, the OFF-state current is also increased to disadvantageously increase the standby current. In a TFT employing amorphous silicon which is mainly applied to an active element for a liquid crystal display, on the other hand, the consumption current comes into question when the TFT is applied to a portable device or a color display, due to a large OFF-state current.
(Problem of Prior Art 24)
In the prior art 24, on the other hand, the gate insulating films 3722 and 3723 which are in amorphous structures are so inferior in crystallinity that these films are increased in thickness to 400 to 500 nm on the TFT side and to at least 200 nm in the dielectric film 3722 on the side of the condensed capacitance part 3711 respectively. Therefore, a large area is required per element for obtaining a sufficient condensed capacitance value, leading to hindrance to high definition. In other words, improvement in numerical aperture is limited.
In the prior art 24, further, the Si channel 3718 is provided in a polycrystalline or amorphous structure, and hence electron mobility in the channel is reduced while resistance values of the lower electrode 3714 for the condensed capacitance part 3711 and the TFT gate 3717 are increased when the same are prepared from general Ta or the like. Therefore, increase in operating speed of the TFT for a driver is limited.
When the lower electrode 3714 for the condensed capacitance part 3711 and the gate 3717 of the TFT 3712 as well as the gate insulating films 3722 and 3723 provided on the upper surfaces thereof are reduced in thickness as shown in FIG. 233, further, it is necessary to form the lower electrode 3714 and the gate 3717 serving as underlayers in flat states. When the lower electrode 3714 and the gate 3717 are made of Al or an Al alloy for attaining low resistance, however, polycrystalline or amorphous structures provided on surfaces thereof may partially define nuclei for growing projections (hillocks) in heat treatment of about 400xc2x0 C.) Thus, a leakage current may be generated in employment. In the prior art 24, therefore, the surfaces of the lower electrode 3714 and the gate 3717 are covered with thick Al2O3 layers by anodization as shown in FIG. 233, for preventing occurrence of hillocks. In this case, however, the number of members is increased with increase of the fabrication steps, and hence the cost is increased.
(Prior Art 25)
A liquid crystal display (LCD) comprising an electrically insulating transparent substrate which is provided thereon with pixel electrodes of liquid crystal elements and thin-film type active elements for driving the liquid crystal elements for respective pixels which are arranged in the form of a matrix is called an active matrix LCD, and forms the mainstream of commercially available liquid crystal displays. The active elements for driving the liquid crystal elements are typically formed by thin-film transistors (TFT).
FIG. 267 is a circuit diagram showing a circuit structure for one pixel in such an active matrix LCD according to prior art 25. Referring to FIG. 267, a liquid crystal element 3853 for one pixel and a TFT 3854 which is connected in series with this liquid crystal element 3853 for driving the same are arranged at an intersection between a signal line 3851 and a scanning line 3852 which are arranged in the form of a matrix. In this example, the TFT 3854 is formed by a MOS field-effect transistor (MOSFET). The series circuit of the liquid crystal element 3853 and the TFT 3854 is interposed between the signal line 3851 and the ground potential, while a gate electrode G which is a control electrode of the TFT 3854 is connected to the scanning line 3852. When the scanning line 3852 is at a high-level potential, the TFT 3854 enters a conducting state so that a picture signal which is carried by the signal line 3851 is written in the liquid crystal element 3853. When the scanning line 3852 is at a low-level potential, on the other hand, the TFT 3854 enters a cutoff state, to hold the picture signal which is written in the liquid crystal element 3853. A number of scanning lines 3852 are successively brought into high levels one by one, for example, for successively updating images displayed by this unit. A holding capacitance 3855 is connected to the liquid crystal element 3853 for supplementing electrostatic capacitance of the liquid crystal element 3853, so that an image signal which is written in the liquid crystal element 3853 is sufficiently held over a period up to next writing.
(Problem of Prior Art 25)
In relation to the TFT 3854 which is employed for the active matrix LCD, known are two types of TFTs including an amorphous silicon TFT and a polysilicon TFT employing amorphous Si polycrystalline Si (polysilicon) for active layers thereof respectively. The term xe2x80x9cactive layerxe2x80x9d in relation to an element such as a transistor indicates a principal part of an element having semiconductor regions of different conductivity types and a junction therebetween for implementing behavior of a main current which is specific to the element.
 less than 1. Problems of Unit Employing Amorphous Silicon TFT greater than 
An active layer of an amorphous silicon TFT can be formed under a low temperature through chemical vapor deposition (CVD), for example. Therefore, the process maximum temperature for forming such an amorphous silicon TFT can be reduced below 400xc2x0 C. Thus, a transparent substrate to be provided with the TFT can be prepared from a low-priced glass substrate having a low withstand temperature. In other words, it is possible to fabricate an amorphous silicon TFT at a low cost.
On the other hand, such an amorphous silicon TFT having an active layer of amorphous Si disadvantageously has a small ON-state current, i.e., current upon conduction, since the active layer has low mobility of about 0.2 to 0.5 cm2/(V.sec). Thus, it is difficult to obtain a high-contrast image having small flicker noise. Further, it is difficult to refine the element due to the small mobility, and hence it is difficult to densely arrange pixels. Consequently, it is difficult to obtain a high-definition image.
Since the active layer is made of amorphous Si, the so-called inverted stagger structure in which a gate electrode is positioned under a channel portion on the side of the transparent substrate is employed. Therefore, it is impossible to use the self-alignment technique of introducing an impurity through the gate electrode serving as a mask. Consequently, the TFT must inevitably be increased in size due to requirement for redundant design of about 5 xcexcm. This also leads to difficulty in provision of a high-definition image. Further, no excellent switching characteristics can be attained since parasitic capacitance between electrodes is increased due to the large-sized TFT, leading to deterioration of picture quality.
In addition, it is difficult to form a circuit for driving the amorphous silicon TFT on a single transparent substrate with the amorphous silicon TFT.
 less than 2. Problems of Unit Employing Polysilicon TFT greater than 
As compared with the amorphous silicon TFT having the aforementioned characteristics, a polysilicon TFT has the following characteristics: The polysilicon TFT has a large ON-state current, i.e., current upon conduction, since its active layer which is made of polycrystalline Si has high mobility of about 10 to 50 cm2/(V.sec.). Therefore, a high-definition image having high contrast and small flicker noise can be easily obtained.
Since the active layer is made of polycrystalline Si, it is possible to employ such a structure that a gate electrode is positioned above a channel portion, i.e., on a side opposite to the transparent substrate. Thus, it is possible to employ the self-alignment structure of introducing an impurity through the gate electrode serving as a mask by preparing the gate electrode from polycrystalline Si, whereby no redundant design is required. This also contributes to a high-definition image. Further, a circuit for driving the polysilicon TFT can be easily formed on a single transparent substrate with the polysilicon TFT, whereby it is possible to advantageously form a miniature unit which is easy to handle.
However, the process maximum temperature of the polysilicon TFT exceeds 600xc2x0 C. so far as the same is fabricated by a conventional method in prior art 25, since it is necessary to form a polycrystalline Si thin film. Thus, an SiO2 (quartz) substrate having a high withstand temperature must be employed as the transparent substrate to be provided with the TFT and the like. Namely, the fabrication cost is increased in a unit employing the polysilicon TFT.
As hereinabove described, a unit employing an amorphous silicon TFT is inferior in picture quality although the same can be fabricated at a low cost, while the polysilicon TFT has a problem of a high fabrication cost although the same has excellent picture quality. In a unit employing a transistor whose active layer is made of single-crystalline Si in place of a polysilicon TFT, further, the fabrication cost is further increased although the picture quality is further improved, while the transistor cannot be provided in the form of a thin film but only a bulk transistor is available, and hence only a reflective LCD can be formed.
(Prior Art 26)
FIGS. 288 to 290 show a semiconductor device of a metal-insulator-semiconductor structure (MIS structure) according to Prior Art 26 employing a cladding system. In the cladding system, an oxide film 3902 is first grown on an Si substrate 3901 to form a first sample 3903 as shown in FIG. 288. Then another silicon wafer sample 3904 is clad thereon as shown in FIG. 289, and the as-clad silicon wafer sample 3904 is scraped to be reduced in thickness as shown in FIG. 290, thereby forming a transistor.
(Prior Art 27)
FIGS. 291 and 292 show a semiconductor device according to Prior Art 27 employing a SIMOX system. According to the SIMOX system, oxygen ions 3912 are ion-implanted in high concentration into a portion of a desired depth in an Si substrate 3911, as shown in FIG. 291. Thereafter a heat treatment is carried out to react the as-implanted oxygen ions 3912 with silicon which is contained in the Si substrate 3911 for forming an SiO2 film 3913 thereby completely dielectric-isolating an upper Si layer 3914 from a lower Si layer 3915 as shown in FIG. 292, so that a heterojunction transistor is formed on the upper surface.
(Prior Art 28)
FIG. 293 illustrates a step of forming a channel in a MOSFET of a general MIS structure or a metal-ferroelectric-semiconductor structure (MFS structure) for serving as an electrically writable/erasable non-volatile memory element according to Prior Art 28. In Prior Art 28, a LOCOS oxide film 3922 and a gate oxide film 3923 are first partially formed on an upper surface of an Si substrate 3921, as shown in FIG. 293. Then, an impurity such as B+ is ion-implanted into the Si substrate 3921 to form a channel, in order to control the threshold value of the MOSFET. At this time, the ion implantation is carried out through the gate oxide film 3923 in the state shown in FIG. 293, or the gate oxide film 3923 is wet-etched after the ion implantation to re-oxidize the Si substrate 3921 for forming a new gate oxide film.
FIG. 294 is a sectional view showing a step of diffusing/forming a source 3924 and a drain 3925 of the general MOSFET according to Prior Art 28. Ions as implanted are generally prepared from P+ or As+ for an NMOS transistor, or B+ or BF2+ for a PMOS transistor. Referring to FIG. 294, numeral 3926 denotes a gate.
FIG. 295 is a sectional view showing the general MOSFET according to Prior Art 28, in a state immediately after formation of an interconnection film 3927. This interconnection film 3927 is generally prepared from Alxe2x80x94Si or Alxe2x80x94Sixe2x80x94Cu. Referring to FIG. 295, numeral 3928 denotes an insulating film of PSG, BPSG or NSG. An Al alloy/TiN laminate structure may be employed in general, since sufficient reliability may not be attained by interconnection with a single Al alloy layer, following refinement of the device.
FIG. 296 is a sectional view showing the MOSFET of a two-layer interconnection film system according to Prior Art 28. Referring to FIG. 296, numeral 3929 denotes a second interconnection film of Alxe2x80x94Si or Alxe2x80x94Sixe2x80x94Cu, and numeral 3931 denotes an interlayer isolation film. The interlayer isolation film 3931, which is an underlayer for the second interconnection film 3929, is preferably flattened since the second interconnection film 3929 may be disconnected if this film 3931 has a step.
In order to flatten the interlayer isolation film 3931, an NSG, PSG or BPSG film or a multilayer oxide film thereof is first deposited by CVD and thereafter coated with a resist or SOG film by a spin coater, to fill up a step portion by a method such as sintering. Thereafter the as-coated material and the multilayer oxide film are simultaneously etched back to form the interlayer isolation film 3931. At this time, it is necessary to maintain the as-coated material and the multilayer oxide film at the same etching rates.
(Prior Art 29)
FIG. 297 is a sectional view showing an EPROM or a flash EPROM according to Prior Art 29. Referring to FIG. 297, numeral 3935 denotes an Si substrate, numeral 3936 denotes a source, numeral 3937 denotes a drain, numeral 3938 denotes a gate insulating film, numeral 3939 denotes a floating gate, numeral 3941 denotes an interlayer isolation film, and numeral 3942 denotes a control gate. The gate insulating film 3938 is formed by an oxide film which is prepared by thermally oxidizing the Si substrate 3935.
(Prior Art 30)
FIG. 298 is a sectional view showing a planar type NPN bipolar transistor according to Prior Art 30. Referring to FIG. 298, numeral 3945 denotes an n-type collector, numeral 3946 denotes a p-type base, and numeral 3947 denotes an n-type emitter. According to Prior Art 30, impurity ions of P or As are implanted into the n-type collector 3945 and the n-type emitter 3947 while impurity ions of B or BF2 are implanted into the p-type base 3946, and these impurities are diffused and activated by a heat treatment.
(Problem of Prior Art 26)
When the cladding system is employed as in Prior Art 26, however, the cost is increased since an operation for cladding two wafers with each other and scraping the same in high accuracy requires a considerable number of steps.
(Problem of Prior Art 27)
When the SIMOX system is employed as in Prior Art 27, on the other hand, considerably high energy ions are implanted and hence crystals are so significantly defected that it is difficult to attain excellent characteristics.
(Problem of Prior Art 28)
When the method of implanting ions through the gate oxide film 3923 in the state shown in FIG. 293 is employed in Prior Art 28, the film quality is deteriorated to easily cause a leakage current and dielectric breakdown due to passage of the high-energy ions through the gate oxide film 3923, although the threshold value can be controlled in high accuracy.
When the method of wet-etching the gate oxide film 3923 after the ion implantation for re-oxidizing the Si substrate 3921 and forming a new gate oxide film, on the other hand, it is difficult to accurately control the threshold value since an impurity (boron) which is implanted into Si is incorporated in the oxide film during the oxidation step, although a high-quality film can be obtained due to the new oxide film formed after the ion implantation.
Thus, it is difficult to improve the quality of the gate oxide film while accurately controlling the threshold value at the same time.
In Prior Art 28, further, impurity concentration generally exceeds1xc3x971020 cmxe2x88x923 after the ion implantation for forming the source 3924 and the drain 3925, to cause a number of defects in the regions provided with the source 3924 and the drain 3925. A heat treatment (annealing) is required in order to recover the defects and activate the impurity. At this time, the impurity is disadvantageously diffused in Si due to the high-temperature treatment, and hence it is difficult to form refined shallow junction. According to Prior Art 28, the gate insulating film 3923 is designed to be about 100 xc3x85 in thickness following refinement of the semiconductor device, while such a gate insulating film 3923 is rather inferior in reliability.
In the interconnection film according to Prior Art 28, sufficient reliability cannot be obtained by interconnection through a single Al alloy layer. In order to solve this problem, an Al alloy/TiN laminate structure is generally employed as hereinabove described. In this case, however, the fabrication steps are complicated to cause increase in cost.
Further, Prior Art 28 requires an oxide film of NS, PSG or BPSG and a coating material of resist or SOG provided on its upper surface for flattening the interlayer isolation film 3931 as shown in FIG. 296, while these materials must be maintained at the same etching rates. Thus, it takes time to adjust the materials.
(Problem of Prior Art 29)
In Prior Art 29, the gate insulating film 3923 is designed to be about 100 xc3x85 in thickness following refinement of the semiconductor device similarly to Prior Art 28, while the gate insulating film 3923 must be improved in reliability in such a thin film forming technique. Thus, awaited is a technique for increasing the thickness of the gate insulating film 3923 and preventing carrier trap in the film interface and occurrence of a leakage current, thereby remarkably improving the insulating film withstand voltage. Particularly in the case of the EPROM or the flash EPROM according to Prior Art 29, the fabrication steps are complicated to increase the cost due to the four-layer structure of the gate portion as shown in FIG. 297.
(Problem of Prior Art 30)
In Prior Art 30, the size of the base 3946 is easily fluctuated due to large dispersion of its thickness D1, to extremely influence on the electric characteristics of the transistor. In the planar type device according to Prior Art 30, it is necessary to reduce the junction capacitance across the base and the collector as well as that across the emitter and the base in order to improve the switching speed of the transistor. However, it is difficult to reduce these junction capacitances since the emitter and the base are formed by. diffusion, as hereinabove described. Further, it is also difficult to reduce the transistor size for a similar reason. FIG. 299 shows a polyemitter transistor structure, which is proposed in relation to a method for solving such a problem. In this structure, an emitter 3947 is formed by a polycrystalline film, so that the junction capacitance across the emitter 3947 and a base 3946 is set at a small value by forming an insulating film 3948. When such a method is employed, it is possible to form an extremely shallow diffusion region of the emitter 3947. However, refinement of the base 3946 is limited since the same is formed by a method similar to that in a planar type device, while the transistor characteristics may be further dispersed as compared with those of the planar type device in view of fabrication steps.
According to a first aspect of the present invention, a method of manufacturing a micromachine comprising a member which is at least partially separated from a base material comprises:
(a) a step of forming a sacrifice layer on the base material,
(b) a step of forming a layer of a prescribed material forming the member on the sacrifice layer,
(c) a step of irradiating the layer of the prescribed material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the prescribed material during or after the step (b), thereby converting the layer of the prescribed material to a single-crystalline layer, and
(d) a step of removing the sacrifice layer after the step (c).
According to a second aspect of the present invention, a method of manufacturing a micromachine comprising a member which is at least partially separated from a base material comprises:
(a) a step of forming a layer of a first material inhibiting progress of etching on a surface of the base material,
(b) a step of forming a layer of a second material forming the member on the layer of the first material,
(c) a step of irradiating the layer of the second material with gas beams of low energy levels causing no sputtering of the second material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the second material during or after the step (b), thereby converting the layer of the second material to a single-crystalline layer, and
(d) a step of selectively etching the base material for exposing the layer of the first material from a back side of the base material after the step (b).
Preferably, the first material is an electrical insulator, and the second material is a semiconductor.
Preferably, the method further comprises (e) a step of selectively introducing an impurity into the single-crystalline layer of the second material, thereby incorporating a distortion sensor into the single-crystalline layer of the second material.
According to a third aspect of the present invention, a method of manufacturing a micromachine comprising a member which is at least partially separated from a base material comprises:
(a) a step of forming a sacrifice layer on the base material,
(b) a step of selectively removing a specific portion of the sacrifice layer,
(c) a step of forming a layer of a prescribed material forming the member on the sacrifice layer and a portion of the base material corresponding to the specific portion,
(d) a step of irradiating the layer of the prescribed material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the prescribed material during or after the step (c), thereby converting the layer of the prescribed material to a single-crystalline layer, and
(e) a step of removing the sacrifice layer after the step (d).
Preferably, the method further comprises (f) a step of selectively forming an opening in the layer of the prescribed material in advance of the step (e), and the step (e) comprises (e-1) a step of removing the sacrifice layer by carrying out etching through the opening after the step (f).
According to a fourth aspect of the present invention, a method of manufacturing a micromachine comprising a member which is at least partially separated from a base material comprises:
(a) a step of forming a first sacrifice layer on the base material,
(b) a step of forming a layer of a first material on the first sacrifice layer,
(c) a step of irradiating the layer of the first material with gas beams of low energy levels causing no sputtering of the first material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the first material during or after the step (b), thereby converting the layer of the first material to a single-crystalline layer,
(d) a step of selectively removing the layer of the first material,
(e) a step of forming a second sacrifice layer on an unremoved remaining portion of the layer of the first material and the first sacrifice layer after the step (d),
(f) a step of selectively removing specific portions of the first and second sacrifice layers while leaving at least the unremoved remaining portion of the layer of the first material resulting from the step (d),
(g) a step of forming a layer of a second material forming the member on the second sacrifice layer and a portion of the base material corresponding to the specific portion,
(h) a step of irradiating the layer of the second material with gas beams of low energy levels causing no sputtering of the second material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the second material during or after the step (g), thereby converting the layer of the second material to a single-crystalline layer, and
(i) a step of removing the first and second sacrifice layers after the step (h).
According to a fifth aspect of the present invention, a method of manufacturing a micromachine comprising a member which is at least partially separated from a base material comprises:
(a) a step of forming a concave portion on an upper surface of the base material,
(b) a step of filling up the concave portion with a sacrifice layer,
(c) a step of forming a layer of a prescribed material forming the member on the sacrifice layer and a portion of the base material corresponding to a peripheral portion of the concave portion,
(d) a step of irradiating the layer of the prescribed material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the prescribed material during or after the step (c), thereby converting the layer of the prescribed material to a single-crystalline layer, and
(e) a step of removing the sacrifice layer after the step (d).
Preferably, the prescribed material is a semiconductor, and the method further comprises (f) a step of selectively introducing an impurity into the single-crystalline layer of the prescribed material, thereby incorporating a distortion sensor into the single-crystalline layer of the prescribed material.
According to a sixth aspect of the present invention, a method of manufacturing a micromachine comprising a member which is at least partially separated from a base material comprises:
(a) a step of forming a concave portion on an upper surface of the base material,
(b) a step of filling up the concave portion with a sacrifice layer,
(c) a step of forming a layer of a first material which is an insulator on the sacrifice layer and a portion of the base material corresponding to a peripheral portion of the concave portion,
(d) a step of forming a layer of a second material which is a semiconductor mainly composing the member on the layer of the first material,
(e) a step of irradiating the layer of the second material with gas beams of low energy levels causing no sputtering of the second material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the second material during or after the step (d), thereby converting the layer of the second material to a single-crystalline layer, and
(f) a step of removing the sacrifice layer after the step (e).
According to a seventh aspect of the present invention, a method of manufacturing a micromachine comprising a step of etching a base material comprises:
(a) a step of forming a layer of a prescribed material on the base material,
(b) a step of irradiating the layer of the prescribed material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the prescribed material during or after the step (a), thereby converting the layer of the prescribed material to a single-crystalline layer having a prescribed crystal orientation provided with high resistance against the etching, and
(c) a step of selectively etching the base material for exposing the layer of the prescribed material from a back side of the base material after the step (b).
Preferably, the base material has a single-crystalline structure and the prescribed material is identical to a material forming the base material, and the method further comprises (d) a step of irradiating the layer of the prescribed material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the prescribed material after the step (c), thereby converting the layer of the prescribed material to a new single-crystalline layer having the same crystal orientation as the base material.
According to an eighth aspect of the present invention, a method of manufacturing a micromachine comprising a step of etching a base material comprises:
(a) a step of forming a masking member on an upper surface of the base material,
(b) a step of selectively removing the masking member,
(c) a step of irradiating an upper surface of a prescribed material forming an upper surface portion of the base material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be formed under an optimum temperature below a crystallization temperature of the prescribed material after the step (b), thereby converting the upper surface portion of the prescribed material to a single-crystalline layer having a prescribed crystal orientation provided with high resistance against the etching,
(d) a step of removing the masking member after the step (c), and
(e) a step of carrying out the etching on the base material from the upper surface of the base material, thereby selectively removing a portion of the base material which is not covered with the single-crystalline layer.
Preferably, the prescribed material forming the upper surface portion of the base material has a single-crystalline structure in advance of the step (c), and the method further comprises (f) a step of irradiating the layer of the prescribed material with gas beams of low energy levels causing no sputtering of the prescribed material from directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline layer to be newly formed under an optimum temperature below a crystallization temperature of the prescribed material after the step (e), thereby converting a single-crystalline layer of the prescribed material to a new single-crystalline layer having the same crystal orientation as that in advance of the step (c).
According to any of the first to eighth aspects of the present invention, the atomic weight of an element forming the gas is preferably lower than the maximum one of the atomic weights of elements forming the material as irradiated.
In the method according to the first aspect of the present invention, the layer of the prescribed material which is formed on the sacrifice layer is irradiated with the gas beams under a prescribed temperature, so that the law of Bravais acts to convert this layer to a single-crystalline layer. It is possible to manufacture a micromachine having a single-crystalline layer on a member such as a beam, a bridge, a diaphragm, a movable part, a hollow vessel or a fluid passage, for example, at least a part of which is not fixed to but separated from a base material, by thereafter removing the sacrifice layer. In the micromachine which is manufactured by this method, therefore, the member separated from the base material has high strength, small abrasion, a high elastic limit, excellent corrosion resistance, and high uniformity of characteristics. Further, the member having a single-crystalline layer is formed on the base material in situ through no junction or incorporation, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the second aspect of the present invention, it is possible to manufacture a micromachine having a single-crystalline layer on a member such as a cantilever, a bridge or a diaphragm, for example, having a part which is fixedly supported by a portion of a base material out of selective etching and another part which is extended in a cavity portion formed by selective etching of the base material. In a micromachine which is manufactured by this method, therefore, the member such as a cantilever or a bridge has high strength, small abrasion, a high elastic limit, excellent corrosion resistance, and high uniformity of characteristics. It is possible to apply large elastic deformation to this member, which is excellent in elastic limit in addition to strength. Therefore, this method is suitable for forming a micromachine which serves as an accelerometer, a stress gauge or a pressure gauge utilizing elastic deformation of this member. Further, the member having a single-crystalline layer is formed on the base material in situ through no junction, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the second aspect of the present invention, it is possible to manufacture a micromachine in which a member such as a cantilever, a bridge or a diaphragm, for example, has a semiconductor single-crystalline layer and is fixedly supported by a base material through an electrical insulator. In a micromachine which is manufactured by this method, therefore, no signal current leaks to the base material when a electronic circuit element such as a sensor is incorporated in the single-crystalline layer of the member such as a bridge, whereby a normal operation of the electronic circuit element is guaranteed.
In the method according to the second aspect of the present invention, it is possible to manufacture a micromachine in which a member such as a cantilever, a bridge or a diaphragm, for example, has a semiconductor single-crystalline layer and a distortion sensor is incorporated into this single-crystalline layer. This micromachine can serve as an accelerometer, a stress gauge or a pressure gauge since deformation of the member such as a cantilever can be detected by the distortion sensor. Further, the member such as a cantilever is excellent in elastic limit in addition to strength due to the single-crystalline layer, whereby it is possible to apply large elastic deformation to this member. Thus, an accelerometer, a stress gauge or a pressure gauge having a wide operating region is implemented. Further, the member such as a cantilever having a single-crystalline layer is formed on the base material in situ through no junction, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the third aspect of the present invention, it is possible to manufacture a micromachine comprising a member, such as a fixed beam, a hollow vessel or a fluid passage, for example, having a part which is fixedly supported by a base material and another part which has a clearance between the same and the base material, so that this member is provided with a single-crystalline layer. In a micromachine which is manufactured by this method, therefore, the member such as a fixed beam is excellent in strength, abrasion resistance, elastic limit, corrosion resistance, and uniformity of characteristics. Due to the excellent elastic limit in addition to strength, it is possible to apply large elastic deformation to this member. Therefore, this method is suitable for forming a micromachine which serves as an electrostatic actuator, for example. Further, this method is also suitable for forming a micromachine which serves as a fluid filter or a fluid valve, for example, since the member is excellent in corrosion resistance. Further, the member having a single-crystalline layer is formed on the base material in situ through no junction, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the third aspect of the present invention, an opening is formed in the material layer to carry out etching through the opening, thereby smoothly removing the sacrifice layer. Therefore, this method is suitable for manufacturing a micromachine which effectuates the opening as such, such as a fluid filter whose opening serves as a fluid passage, for example.
In the method according to the fourth aspect of the present invention, it is possible to manufacture a micromachine comprising a member such as a hollow vessel or a fluid passage, for example, having a part which is fixedly supported by a base material and another part which has a hollow portion between the same and the base material, and another member inserted in the hollow portion, so that both of the members have single-crystalline layers. These members are excellent in strength, abrasion resistance, elastic limit, corrosion resistance, and uniformity of characteristics, due to the single-crystalline layers. This method is suitable for forming a micromachine which serves as a fluid valve, for example, since these members are excellent in corrosion resistance and abrasion resistance. Further, it is possible to apply large deformation to the member which is inserted in the hollow portion since the same is excellent in elastic limit in addition to strength. Therefore, this method is also suitable for forming a micromachine which serves as a pressure gauge having an oscillator which is inserted in the hollow portion. Further, the members having single-crystalline layers are formed on the base material in situ through no junction, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the fifth aspect of the present invention, it is possible to manufacture a micromachine provided with a single-crystalline layer on a member such as a cantilever, a bridge or a diaphragm, for example, having a part which is fixedly supported by a peripheral portion of a concave portion of a base material and another part which is extended in a cavity portion defined by the concave portion of the base material. In the micromachine which is manufactured by this method, therefore, the member such as a cantilever or a bridge has high strength, small abrasion, a high elastic limit, excellent corrosion resistance, and high uniformity of characteristics. It is possible to apply large elastic deformation to this member, which is excellent in elastic limit in addition to strength. Therefore, this method is suitable for forming a micromachine which serves as an accelerometer, a stress gauge or a pressure gauge utilizing elastic deformation of this member. Further, the member having a single-crystalline layer is formed on the base material in situ through no junction, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the fifth aspect of the present invention, it is possible to manufacture a micromachine provided with a member such as a cantilever, a bridge or a diaphragm, for example, which has a semiconductor layer so that a distortion sensor is incorporated in this single-crystalline layer. This micromachine can serve as an accelerometer, a stress gauge or a pressure gauge since deformation of the member such as a cantilever can be detected by the distortion sensor. Further, it is possible to apply large elastic deformation to the member such as a cantilever, which is excellent in elastic limit in addition to strength due to the single-crystalline layer. Thus, an accelerometer, a stress gauge or a pressure gauge having a wide operating region is implemented. Further, the member having a single-crystalline layer is formed on the base material in situ through no junction, whereby a highly accurate micromachine which is easy to manufacture is implemented.
In the method according to the sixth aspect of the present invention, it is possible to manufacture a micromachine provided with a member such as a cantilever, a bridge or a diaphragm, for example, which has a semiconductor single-crystalline layer and is fixedly supported by a base material through an electrical insulator. In a micromachine which is manufactured by this method, therefore, no signal current leaks to the base material when an electronic circuit element such as a sensor is incorporated into the single-crystalline layer of the member such as a bridge, whereby a normal operation of the electronic circuit element is guaranteed.
In the method according to the seventh aspect of the present invention, a single-crystalline layer having a crystal orientation suppressing progress of etching is formed on a base material in selective etching of the base material, so that this single-crystalline layer is utilized as an etching stopper. Further, the single-crystalline layer is formed by beam irradiation, whereby a single-crystalline layer of a prescribed material, a prescribed crystal orientation and a prescribed crystal structure can be formed on an arbitrary base material in situ with no dependency on the material of the base material, presence/absence of crystallinity, sizes of crystal grains, the crystal structure and the crystal orientation. Thus, it is possible to easily manufacture a micromachine including a single-crystalline layer as an element and having a complicated structure.
In the method according to the seventh aspect of the present invention, the crystal orientation of the single-crystalline layer of a prescribed material is converted to be identical to that of the base material after completion of utilization as an etching stopper. According to this method, therefore, it is possible to manufacture a micromachine having a complicated structure by a material having a constant substance and a constant crystal orientation. In a micromachine which is manufactured by this method, the base material has an integral structure as if the same is grown into a complicated shape. According to this method, therefore, it is possible to manufacture a micromachine which is excellent in strength and uniformity of characteristics of respective parts in particular.
In the method according to the eighth aspect of the present invention, a single-crystalline layer having a crystal orientation suppressing progress of etching is formed on a base material in selective etching of the base material, so that this single-crystalline layer is utilized as an etching mask. Further, the single-crystalline layer is formed by beam irradiation, whereby a single-crystalline layer of a prescribed material, a prescribed crystal orientation and a prescribed. crystal structure can be formed on an upper surface of an arbitrary base material in situ with no dependency on the substance of the base material, presence/absence of crystallinity, sizes of crystal grains, the crystal structure and the crystal orientation. Thus, it is possible to easily and accurately manufacture a micromachine having a complicated structure.
In the method according to the eighth aspect of the present invention, the crystal orientation of the single-crystalline layer of a prescribed material is converted to be identical to that of the base material after completion of utilization as an etching mask. According to this method, therefore, it is possible to manufacture a micromachine having no trace of the etching mask. Particularly when the overall base material has a single-crystalline structure, it is possible to manufacture a micromachine having a complicated structure with a material having a constant substance and a constant crystal orientation. In this case, it is possible to manufacture a micromachine which is excellent in strength and uniformity of characteristics of respective parts in particular.
In the method according to any of the first to eighth aspects of the present invention, the atomic weight of the element forming the gas beam is lower than the maximum one of the atomic weights of the elements forming the material as irradiated, whereby most of the atoms forming the as-applied gas are rearwardly scattered on the surface or in the vicinity of the material as irradiated, to hardly remain in this material. Therefore, it is possible to obtain a single-crystalline thin film having a small amount of impurities.
Accordingly, an object of the present invention is to provide a method of manufacturing a micromachine, which can easily and accurately manufacture a micromachine of a complicated structure provided with a single-crystalline substance as its member.
According to a ninth aspect of the present invention, a solar cell comprises a substrate, a first conductivity type first semiconductor film which is formed on an upper surface of the substrate from a material different from that for the substrate, a first electrode which is connected to the first semiconductor film, a second conductivity type second semiconductor film which is formed on an upper surface of the first semiconductor film, and a second electrode which is connected to the second semiconductor film, and the first and second semiconductor films are formed by single-crystalline films.
According to a tenth aspect of the present invention, a solar cell at least comprises a first heterojunction part having a first conductivity type first semiconductor film and a second conductivity type second semiconductor film which is formed on an upper surface of the first semiconductor film, and a second heterojunction part having a first conductivity type third semiconductor film which is formed on an upper surface of the second semiconductor film and a second conductivity type fourth semiconductor film which is formed on an upper surface of the third semiconductor film, and the heterojunction parts are arranged from that having a larger forbidden bandwidth along a direction of progress of light, while the first, second, third and fourth semiconductor films are formed by single-crystalline films.
Preferably, an interlayer conductor having a thickness capable of transmitting light is interposed between the heterojunction parts.
Preferably, the interlayer conductor is prepared from a metal having an ohmic junction property with respect to the heterojunction parts.
Preferably, the second semiconductor film which is arranged on one side of the interlayer conductor is different in crystal orientation from the third semiconductor film which is arranged on another side of the interlayer conductor.
According to the ninth or tenth aspect of the present invention, each of the single-crystalline films is preferably formed by supplying reaction gases under a low temperature below a crystalline temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
According to the ninth or tenth aspect of the present invention, each of the single-crystalline films is preferably formed by applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature of a previously formed amorphous or polycrystalline thin film.
According to the ninth or tenth aspect of the present invention, each of the single-crystalline films is preferably prepared from a group II-VI compound.
According to the ninth or tenth aspect of the present invention, each of the single-crystalline films is preferably prepared from a group III-V compound.
The present invention is also directed to a method of manufacturing a solar cell. According to an eleventh aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor film and an electrode thereof on an upper surface of a substrate of a material which is different from that for the first semiconductor film, and a second step of forming a second conductivity type second semiconductor film and an electrode thereof on an upper surface of the first semiconductor film, and each of the first and second steps includes a step of supplying reaction gases under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the first or second semiconductor film of a single-crystalline film.
According to a twelfth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor film and an electrode thereof on an upper surface of a substrate of a material which is different from that for the first semiconductor film, and a second step of forming a second conductivity type second semiconductor film and an electrode thereof on an upper surface of the first semiconductor film, and each of the first and second steps includes a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature thereby forming the first or second semiconductor film of a single-crystalline film.
According to a thirteenth aspect of the present invention, a method of manufacturing a solar cell at least comprises a first step of forming a first conductivity type first semiconductor film and an electrode thereof on an upper surface of a substrate of a material which is different from that for the first semiconductor film, a second step of forming a second conductivity type second semiconductor film on an upper surface of the first semiconductor film thereby forming a first heterojunction part, a third step of forming a first conductivity type third semiconductor film on an upper surface of the second semiconductor film, and a fourth step of forming a second conductivity type fourth semiconductor film and an electrode thereof on an upper surface of the third semiconductor film thereby forming a second heterojunction part, and each of the first, second, third and fourth steps comprises a step of supplying reaction gases under a low temperature below a crystalline temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the first, second, third or fourth semiconductor film of a single-crystalline film.
According to a fourteenth aspect of the present invention, a method of manufacturing a solar cell at least comprises a first step of forming a first conductivity type first semiconductor film and an electrode thereof on an upper surface of a substrate of a material which is different from that for the first semiconductor film, a second step of forming a second conductivity type second semiconductor film on an upper surface of the first semiconductor film thereby forming a first heterojunction part, a third step of forming a first conductivity type third semiconductor film on an upper surface of the second semiconductor film, and a fourth step of forming a second conductivity type fourth semiconductor film and an electrode thereof on an upper surface of the third semiconductor film thereby forming a second heterojunction part, and each of the first, second, third and fourth steps comprises a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the first, second, third or fourth semiconductor film of a single-crystalline film.
According to the thirteenth or fourteenth aspect of the present invention, the method preferably further comprises a step of forming an interlayer conductor of a metal having an ohmic junction property with respect to the heterojunction parts between the heterojunction parts in a thickness capable of transmitting light between the second and third steps.
According to the thirteenth or fourteenth aspect of the present invention, the third semiconductor film is formed to have a crystal orientation which is different from that of the second semiconductor film in the third step.
According to the ninth aspect of the present invention, the respective semiconductor films are formed by single-crystalline films, whereby it is possible to remarkably improve electron mobility upon entrance of light, thereby improving electrical properties. Further, it is possible to easily add impurities since the semiconductor films are single-crystalline.
According to the tenth aspect of the present invention, it is possible to remarkably improve electron mobility upon entrance of light thereby improving electrical properties, by employing a tandem structure for absorbing light in a wide range while forming the respective semiconductor films by single-crystalline films.
According to the tenth of the present invention, the interlayer conductor is interposed between the heterojunction parts, whereby the resistance value of the solar cell can be reduced as compared with a case of merely generating a tunnel current in an interface between heterojunction parts. Particularly according to the tenth aspect of the present invention, it is possible to remarkably reduce the resistance value by providing an ohmic junction property. According to the tenth aspect, further, the interlayer conductor is formed in a thickness capable of transmitting light, whereby light passing through one of the heterojunction parts can be introduced into the other heterojunction part as much as possible, thereby improving light absorptivity.
According to the tenth aspect of the present invention, further, the crystal orientation of the second semiconductor film which is arranged on one side of the interlayer conductor is made different from that of the third semiconductor film which is provided on another side, whereby an ohmic junction of low resistance can be obtained.
In accordance with each of the first to fourteenth aspects of the present invention, it is possible to easily form a single-crystalline film having a regulated crystal orientation in a free thickness under a low temperature even if the underlayer is not of a single-crystalline structure. In particular, the thicknesses of the semiconductor films can be reduced to degrees necessary and insufficient for a solar cell, thereby minimizing the member cost.
According to the ninth or tenth aspect of the present invention, the number of photons which can be absorbed in a semiconductor material is generally reduced as the forbidden bandwidth is increased, while the ratio of an energy component which can be extracted to the exterior from energy of the as-absorbed photons is increased in proportion to the forbidden bandwidth. Thus, it is understood that correlation is caused between conversion efficiency and the forbidden bandwidth when the number of photons which can be absorbed is multiplied by the ratio of the energy component of the photons which can be extracted to the exterior. It is known that the forbidden bandwidth of a group II-VI compound such as CdS or CdTe or a group III-V compound such as GaAs exhibits the highest conversion efficiency in such correlation. In consideration of this, a group II-VI or III-V compound is employed as a material for each semiconductor film, whereby the absorption coefficient and wavelength characteristics on absorption ends are remarkably improved.
Accordingly, an object of the present invention is to provide a solar cell and a method of manufacturing the same, which can facilitate addition of an impurity and control of an amount of introduction thereof through a low-priced substrate.
According to a fifteenth aspect of the present invention, a solar cell comprises a first conductivity type first semiconductor layer which is arranged on a photoreceiving side, a second conductivity type second semiconductor layer which is arranged on a light travelling direction side beyond the first semiconductor layer, and an intrinsic semiconductor layer of an amorphous film which is interposed between the first and second semiconductor layers, and the first semiconductor layer is formed by a single-crystalline film.
According to a sixteenth aspect of the present invention, a solar cell comprises a first conductivity type first semiconductor layer which is arranged on a photoreceiving side, a second conductivity type second semiconductor layer which is arranged on a light travelling direction side beyond the first semiconductor layer, and an intrinsic semiconductor layer of an amorphous film which is interposed between the first and second semiconductor layers, and the first semiconductor layer is formed by a polycrystalline film.
According to the fifteenth or sixteenth aspect of the present invention, the second semiconductor layer is preferably formed by a single-crystalline film.
According to the fifteenth or sixteenth aspect of the present invention, the second semiconductor layer is preferably formed by a polycrystalline film.
According to a seventeenth aspect of the present invention, a solar cell comprises a first conductivity type first semiconductor layer which is arranged on a photoreceiving side, an intrinsic semiconductor layer of an amorphous film which is arranged on a light travelling direction side beyond the first semiconductor layer, a second conductivity type second semiconductor layer which is arranged on a light travelling direction side beyond the intrinsic semiconductor layer, a first conductivity type third semiconductor layer which is arranged on a light travelling direction side of the second semiconductor layer, and another intrinsic semiconductor layer of an amorphous film which is interposed between the first and second semiconductor layers, and the second and third semiconductor layers are formed by single-crystalline films.
According to an eighteenth aspect of the present invention, a solar cell comprises a first conductivity type first semiconductor layer which is arranged on a photoreceiving side, an intrinsic semiconductor layer of an amorphous film which is arranged on a light travelling direction side beyond the first semiconductor layer, a second conductivity type second semiconductor layer which is arranged on a light travelling direction side beyond the intrinsic semiconductor layer, a first conductivity type third semiconductor layer which is arranged on a light travelling direction side of the second semiconductor layer, and another intrinsic semiconductor layer of an amorphous film which is interposed between the first and second semiconductor layers, and the second and third semiconductor layers are formed by polycrystalline films.
According to the seventeenth or eighteenth aspect of the present invention, the first semiconductor layer is preferably formed by a single-crystalline film.
According to the seventeenth or eighteenth aspect of the present invention, the first semiconductor layer is preferably formed by a polycrystalline film.
According to the fifteenth, sixteenth, seventeenth or eighteenth aspect of the present invention, the first semiconductor layer is preferably formed to be smaller in thickness than each intrinsic semiconductor layer.
According to the fifteenth, sixteenth, seventeenth or eighteenth aspect of the present invention, each single-crystalline film is preferably formed by supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
According to the fifteenth, sixteenth, seventeenth or eighteenth aspect of the present invention, each single-crystalline film is preferably formed by irradiating a previously formed amorphous thin film with beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature.
According to the fifteenth, sixteenth, seventeenth or eighteenth aspect of the present invention, each polycrystalline film is preferably formed by supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
According to the fifteenth, sixteenth, seventeenth or eighteenth aspect of the present invention, each polycrystalline film is preferably formed by irradiating a previously formed amorphous thin film with beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature.
The present invention is also directed to a method of manufacturing a solar cell. According to a nineteenth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for forming the first semiconductor layer of a single-crystalline film.
According to a twentieth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for forming the first semiconductor layer of a single-crystalline film.
According to a twenty-first aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for forming the first semiconductor layer of a polycrystalline film.
According to an twenty-second aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for forming the first semiconductor layer of a polycrystalline film.
According to the nineteenth, twentieth, twenty-first or twenty-second aspect of the present invention, the third step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for forming the second semiconductor layer of a single-crystalline film.
According to the nineteenth, twentieth, twenty-first or twenty-second aspect of the present invention, the third step preferably includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for forming the second semiconductor layer of a single-crystalline film.
According to the nineteenth, twentieth, twenty-first or twenty-second aspect of the present invention, the third step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for forming the second semiconductor layer of a polycrystalline film.
According to the nineteenth, twentieth, twenty-first or twenty-second aspect of the present invention, the third step preferably includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for forming the second semiconductor layer of a polycrystalline film.
According to a twenty-third aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the third step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for forming the second semiconductor layer of a single-crystalline film.
According to a twenty-fourth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the third step includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for forming the second semiconductor layer of a single-crystalline film.
According to an twenty-fifth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the third step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for forming the second semiconductor layer of a polycrystalline film.
According to a twenty-sixth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, and a third step of forming a second conductivity type second semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the third step includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for forming the second semiconductor layer of a polycrystalline film.
According to a twenty-seventh aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, a third step of forming a second semiconductor layer of a second conductivity type single-crystalline film on an upper surface of the intrinsic semiconductor layer, and a fourth step of forming a third semiconductor layer of a first conductivity type single-crystalline film and an electrode thereof on an upper surface of the second semiconductor layer, and the third step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for carrying out single crystallization and forming the semiconductor layer.
According to a twenty-eighth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, a third step of forming a second semiconductor layer of a second conductivity type single-crystalline film on an upper surface of the intrinsic semiconductor layer, and a fourth step of forming a third semiconductor layer of a first conductivity type single-crystalline film and an electrode thereof on an upper surface of the second semiconductor layer, and the third step includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for single-crystallizing the thin film and forming the second semiconductor layer.
According to the twenty-seventh or twenty-eighth aspect of the present invention, the fourth step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for carrying out single crystallization and forming the third semiconductor layer.
According to the twenty-seventh or twenty-eighth aspect of the present invention, the fourth step preferably includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for single-crystallizing the thin film and forming the third semiconductor layer.
According to a twenty-ninth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, a third step of forming a second semiconductor layer of a second conductivity type polycrystalline film on an upper surface of the intrinsic semiconductor layer, and a fourth step of forming a third semiconductor layer of a first conductivity type polycrystalline film and an electrode thereof on an upper surface of the second semiconductor layer, and the third step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for carrying out polycrystallization and forming the second semiconductor layer.
According to a thirtieth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of a substrate consisting of a material which is different from that for the first semiconductor layer, a second step of forming an intrinsic semiconductor layer of an amorphous film on an upper surface of the first semiconductor layer, a third step of forming a second semiconductor layer of a second conductivity type polycrystalline film on an upper surface of the intrinsic semiconductor layer, and a fourth step of forming a third semiconductor layer of a first conductivity type polycrystalline film and an electrode thereof on an upper surface of the second semiconductor layer, and the third step includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for polycrystallizing the thin film and forming the second semiconductor layer.
According to the twenty-ninth or thirtieth aspect of the present invention, the fourth step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for carrying out polycrystallization and forming the third semiconductor layer.
According to the twenty-ninth or thirtieth aspect of the present invention, the fourth step preferably includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for polycrystallizing the thin film and forming the third semiconductor layer.
According to the twenty-seventh, twenty-eighty, twenty-ninth or thirtieth aspect of the present invention, the first step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for carrying out single crystallization and forming the first semiconductor layer.
According to the twenty-seventh, twenty-eighth or twenty-ninth or thirtieth aspect of the present invention, the first step preferably includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for single-crystallizing the thin film and forming the first semiconductor layer.
According to the twenty-seventh, twenty-eighth, twenty-ninth or thirtieth aspect of the present invention, the first step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for carrying out polycrystallization and forming the first semiconductor layer.
According to the twenty-seventh, twenty-eighth, twenty-ninth or thirtieth aspect of the present invention, the first step preferably includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for polycrystallizing the thin film and forming the first semiconductor layer.
According to a thirty-first aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a third semiconductor layer of a first conductivity type single-crystalline film on an upper surface of a back substrate consisting of a material which is different from that for the third semiconductor layer, a second step of forming a second semiconductor layer of a second conductivity type single-crystalline film on an upper surface of the third semiconductor layer, a third step of forming an intrinsic semiconductor layer of an amorphous film on an upper side of the second semiconductor layer, and a fourth step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for carrying out single crystallization and forming the third semiconductor layer.
According to an twenty-second aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a third semiconductor layer of a first conductivity type single-crystalline film on an upper surface of a back substrate consisting of a material which is different from that for the third semiconductor layer, a second step of forming a second semiconductor layer of a second conductivity type single-crystalline film on an upper surface of the third semiconductor layer, a third step of forming an intrinsic semiconductor layer of an amorphous film on an upper side of the second semiconductor layer, and a fourth step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for single-crystallizing the thin film and forming the third semiconductor layer.
According to the thirty-first or thirty-second aspect of the present invention, the second step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for carrying out single crystallization and forming the second semiconductor layer.
According to the thirty-first or thirty-second aspect of the present invention, the second step preferably includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for single-crystallizing the thin film and forming the second semiconductor layer.
According to a thirty-third aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a third semiconductor layer of a first conductivity type polycrystalline film on an upper surface of a back substrate consisting of a material which is different from that for the third semiconductor layer, a second step of forming a second semiconductor layer of a second conductivity type polycrystalline film on an upper surface of the third semiconductor layer, a third step of forming an intrinsic semiconductor layer of an amorphous film on an upper side of the second semiconductor layer, and a fourth step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for carrying out polycrystallization and forming the third semiconductor layer.
According to a thirty-fourth aspect of the present invention, a method of manufacturing a solar cell comprises a first step of forming a third semiconductor layer of a first conductivity type polycrystalline film on an upper surface of a back substrate consisting of a material which is different from that for the third semiconductor layer, a second step of forming a second semiconductor layer of a second conductivity type polycrystalline film on an upper surface of the third semiconductor layer, a third step of forming an intrinsic semiconductor layer of an amorphous film on an upper side of the second semiconductor layer, and a fourth step of forming a first conductivity type first semiconductor layer and an electrode thereof on an upper surface of the intrinsic semiconductor layer, and the first step includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for polycrystallizing the thin film and forming the third semiconductor layer.
According to the thirty-third or thirty-fourth aspect of the present invention, the second step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for carrying out polycrystallization and forming the second semiconductor layer.
According to the thirty-third or thirty-fourth aspect of the present invention, the second step preferably includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for polycrystallizing the thin film and forming the second semiconductor layer.
According to the thirty-first, thirty-second, thirty-third or thirty-fourth aspect of the present invention, the fourth step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for carrying out single crystallization and forming the first semiconductor layer.
According to the thirty-first, thirty-second, thirty-third or thirty-fourth aspect of the present invention, the fourth step preferably includes a step of previously forming an amorphous thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature of less than a crystallization temperature for single-crystallizing the thin film and forming the first semiconductor layer.
According to the thirty-first, thirty-second, thirty-third or thirty-fourth aspect of the present invention, the fourth step preferably includes a step of supplying a reaction gas under a low temperature of less than a crystallization temperature and simultaneously applying a beam from one direction which is perpendicular to a densest crystal plane for carrying out polycrystallization and forming the first semiconductor layer.
According to the thirty-first, thirty-second, thirty-third or thirty-fourth aspect of the present invention, the fourth step preferably includes a step of previously forming an amorphous thin film and applying a beam from one direction which is perpendicular to a densest crystal plane under a low temperature of less than a crystallization temperature for polycrystallizing the thin film and forming the first semiconductor layer.
According to any of the fifteenth to twenty-second and twenty-seventh to thirty-fourth aspects of the present invention, the first semiconductor layer provided on the photoreceiving side of the solar cell having a p-i-n structure is formed by a single-crystalline or polycrystalline film and the intrinsic semiconductor layer provided on the light travelling direction side is formed by an amorphous film, whereby long-wave light can be mainly absorbed by the first semiconductor layer provided on the photoreceiving side and short-wave light can be mainly absorbed by the intrinsic semiconductor layer. Thus, it is possible to efficiently absorb light of a wider wavelength region as compared with the prior art provided with both layers of amorphous films.
According to any of the fifteenth, seventeenth, nineteenth, twentieth and twenty-seventh to thirty-fourth aspects of the present invention, in particular, it is possible to extremely reduce defect density as well as the rate of annihilation of minority carriers resulting from recombination by preparing the surface layer from a single-crystalline film, thereby effectively extracting the minority carriers.
Further, it is possible to prevent the respective semiconductor layers from deterioration caused by time change, by crystallizing the semiconductor layers in the aforementioned manner.
Long-wave light which cannot be absorbed by the first semiconductor layer of a single-crystalline or polycrystalline film but passes through the same can be further absorbed by the second semiconductor layer according to any of the fifteenth, sixteenth and nineteenth to twenty-second aspects of the present invention, or by the second and third semiconductor layers according to any of the seventeenth, eighteenth and twenty-seventh to thirty-fourth aspects of the present invention, whereby absorption properties for a longer wavelength side can be improved. According to any of the seventeenth, eighteenth and twenty-seventh to thirty-fourth aspects of the present invention, in particular, it is possible to attain absorption properties for light of a wider wavelength region due to the employment of a tandem structure.
According to any of the fifteenth to eighteenth aspects of the present invention, the semiconductor layer provided on the photoreceiving side is so reduced in thickness that part of light as received, i.e., part of mainly long-wave light, is absorbed and thereafter the light can pass through the intrinsic semiconductor layer as much as possible, thereby improving absorption efficiency for light of a shorter wavelength region in the intrinsic semiconductor layer. Further, the intrinsic semiconductor layer formed by an amorphous layer originally has an excellent absorption coefficient which is not damaged even if this layer is reduced in thickness, whereby the overall solar cell can be easily reduced in thickness.
According to any of the fifteenth to thirty-fourth aspects of the present invention, crystallization can be carried out under low temperature environment and hence no heat resistance is required for the underlayer, whereby crystalline films can be formed on a low-priced substrate of glass or the like, for example. Further, the thickness of each semiconductor layer of a single-crystalline or polycrystalline film can be freely set absolutely similarly to formation of an amorphous film, whereby the thickness of this semiconductor layer can be extremely reduced as compared with the prior art which grows/forms each semiconductor film from a wafer of a single-crystalline or polycrystalline film. Thus, it is possible to minimize the thickness of the semiconductor layer within a range of sufficient light absorptivity for serving as a crystalline film, thereby reducing the overall solar cell in thickness. Thus, it is possible to extremely reduce the member cost while improving the characteristics by each crystallized semiconductor layer.
Accordingly, an object of the present invention is to obtain a solar cell having high conversion efficiency and small deterioration at a low cost.
According to a thirty-fifth aspect of the present invention, a semiconductor device which is a memory device capable of volatile or nonvolatile storage comprises a semiconductor substrate, a transistor part which is formed on a surface of the semiconductor substrate and provided with an internal wire on its upper surface portion, a dielectric film which is formed on an upper surface of the internal wire of the transistor part, and an upper electrode which is formed on an upper surface of the dielectric film, and the dielectric film is formed by a single-crystalline film.
According to a thirty-sixth aspect of the present invention, a semiconductor device which is a memory device capable of nonvolatile storage comprises a first conductivity type semiconductor substrate, second conductivity type first and second diffusion regions which are selectively formed on a surface of the semiconductor substrate, a first insulating film which is formed on a portion of the semiconductor substrate located between the first and second diffusion regions, a floating gate which is formed on the first insulating film, a second insulating film which is formed on the floating gate, and a control gate which is formed on the second insulating film, and the floating gate is formed by a single-crystalline film.
According to a thirty-seventh aspect of the present invention, a semiconductor device which is a memory device capable of nonvolatile storage comprises a first conductivity type semiconductor substrate, second conductivity type first and second diffusion regions which are selectively formed on a surface of the semiconductor substrate, a first insulating film which is formed on a portion of the semiconductor substrate located between the first and second diffusion regions, a floating gate which is formed on the first insulating film, a second insulating film which is formed on the floating gate, and a control gate which is formed on the second insulating film, and the second insulating film is formed by a single-crystalline film.
According to the thirty-fifth, thirty-sixth or thirty-seventh aspect of the present invention, the single-crystalline film is preferably formed by supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
According to the thirty-fifth, thirty-sixth or thirty-seventh aspect of the present invention, the single-crystalline film is preferably formed by applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature of a previously formed amorphous or polycrystalline thin film.
According to a thirty-eighth aspect of the present invention, a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprises a first substrate, a plurality of second substrates which are arranged in parallel above the first substrate, first and second diffusion regions which are selectively formed on upper layer portions of the second substrates, an active region which is formed between the first and second diffusion regions, a gate insulating film which is formed at least on an upper surface of the active region, and a gate electrode which is formed on an upper surface of the gate insulating film, and the gate insulating film is formed by a single-crystalline film consisting of a ferroelectric substance.
According to a thirty-ninth aspect of the present invention, a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprises a first substrate, a plurality of second substrates which are arranged in parallel above the first substrate, first and second diffusion regions which are selectively formed on upper layer portions of the second substrates, an active region which is formed between the first and second diffusion regions, a gate insulating film which is formed at least on an upper surface of the active region, and a gate electrode which is formed on an upper surface of the gate insulating film, and the gate insulating film consists of a ferroelectric substance, while the first and second diffusion regions and the active region are formed by single-crystalline films.
According to the thirty-eighth or thirty-ninth aspect of the present invention, substrate electrodes are preferably formed on the second substrates, and the substrate electrodes are formed by single-crystalline films.
According to the thirty-eighth or thirty-ninth aspect of the present invention, clearances are preferably defined between the plurality of second substrates, insulating films are preferably formed in the clearances, and each single-crystalline film is preferably formed by applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature of a previously formed amorphous or polycrystalline thin film.
According to the thirty-eighth or thirty-ninth aspect of the present invention, clearances are preferably defined between the plurality of second substrates, insulating films are preferably formed in the clearances, and each single-crystalline film is preferably formed by supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
According to a fortieth aspect of the present invention, a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprising a plurality of memory cells comprises a semiconductor substrate, diffusion and active regions which are alternately formed above the semiconductor substrate, a gate insulating film which is formed at least on upper surfaces of the respective active regions, and a gate electrode which is formed on an upper surface of the gate insulating film, and the gate insulating film is formed by a single-crystalline film consisting of a ferroelectric substance.
According to a forty-first aspect of the present invention, a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprising a plurality of memory cells comprises a semiconductor substrate, diffusion and active regions which are alternately formed above the semiconductor substrate, a gate insulating film which is formed at least on upper surfaces of the respective active regions, and a gate electrode which is formed on an upper surface of the gate insulating film, and the diffusion and active regions are formed by single-crystalline films.
According to any of the thirty-eighth to forty-first aspects of the present invention, each single-crystalline film is preferably formed by applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature of a previously formed amorphous or polycrystalline thin film.
According to any of the thirty-eighth to forty-first aspects of the present invention, each single-crystalline film is preferably formed by supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
The present invention is also directed to a method of fabricating a semiconductor device. According to an forty-second aspect of the present invention, a method of fabricating a semiconductor device which is a memory device capable of volatile or nonvolatile storage comprises a step of forming a transistor part having an internal wire on its upper surface portion on a surface of a semiconductor substrate, a step of forming a dielectric film on an upper surface of the internal wire of the transistor part, and a step of forming an upper electrode on an upper surface of the dielectric film, and the step of forming the dielectric film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the dielectric film consisting of a single-crystalline film.
According to a forty-third aspect of the present invention, a method of fabricating a semiconductor device which is a memory device capable of volatile or nonvolatile storage comprises a step of forming a transistor part having an internal wire on its upper surface portion on a surface of a semiconductor substrate, a step of forming a dielectric film on an upper surface of the internal wire of the transistor part, and a step of forming an upper electrode on an upper surface of the dielectric film, and the step of forming the dielectric film includes a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature thereby forming the dielectric film consisting of a single-crystalline film.
According to a forty-fourth aspect of the present invention, a method of fabricating a semiconductor device which is a memory device capable of nonvolatile storage comprises a step of selectively forming first and second diffusion regions on a surface of a semiconductor substrate, a step of forming a first insulating film on a portion of the semiconductor substrate located between the first and second diffusion regions, a step of forming a floating gate on the first insulating film, a step of forming a second insulating film on the floating gate, and a step of forming a control gate on the second insulating film, and the step of forming the floating gate includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the floating gate consisting of a single-crystalline film.
According to an forty-fifth aspect of the present invention, a method of fabricating a semiconductor device which is a memory device capable of nonvolatile storage comprises a step of selectively forming first and second diffusion regions on a surface of a semiconductor substrate, a step of forming a first insulating film on a portion of the semiconductor substrate located between the first and second diffusion regions, a step of forming a floating gate on the first insulating film, a step of forming a second insulating film on the floating gate, and a step of forming a control gate on the second insulating film, and the step of forming the floating gate includes a step of previously forming an amorphous or polycrystalline film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature thereby forming the floating gate consisting of a single-crystalline film.
According to a forty-sixth aspect of the present invention, a method of fabricating a semiconductor device which is a memory device capable of nonvolatile storage comprises a step of selectively forming first and second diffusion regions on a surface of a semiconductor substrate, a step of forming a first insulating film on a portion of the semiconductor substrate located between the first and second diffusion regions, a step of forming a floating gate on the first insulating film, a step of forming a second insulating film on the floating gate, and a step of forming a control gate on the second insulating film, and the step of forming the second insulating film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the second insulating film consisting of a single-crystalline film.
According to a forty-seventh aspect of the present invention, a method of fabricating a semiconductor device which is a memory device capable of nonvolatile storage comprises a step of selectively forming first and second diffusion regions on a surface of a semiconductor substrate, a step of forming a first insulating film on a portion of the semiconductor substrate located between the first and second diffusion regions, a step of forming a floating gate on the first insulating film, a step of forming a second insulating film on the floating gate, and a step of forming a control gate on the second insulating film, and the step of forming the second insulating film includes a step of previously forming an amorphous or polycrystalline film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature thereby forming the second insulating film consisting of a single-crystalline film.
According to a forty-eighth aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprises a step of forming a plurality of second substrates, which are separated from each other through insulating films, in parallel above a first substrate, a step of forming first and second diffusion regions, which are separated from each other through active regions, on upper layer portions of the second substrates, a step of forming a gate insulating film over upper surfaces of a plurality of active regions, the first and second diffusion regions and the insulating films, and a step of forming a gate electrode on the gate insulating film, and the step of forming the gate insulating film includes a step of previously forming an amorphous or polycrystalline film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions of the amorphous or polycrystalline thin film under a low temperature below a crystallization temperature thereby forming the gate insulating film consisting of a single-crystalline film.
According to a forty-ninth aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprises a step of forming a plurality of second substrates, which are separated from each other through insulating films, in parallel above a first substrate, a step of forming first and second diffusion regions, which are separated from each other through active regions, on upper layer portions of the second substrates, a step of forming a gate insulating film over upper surfaces of a plurality of active regions, the first and second diffusion regions and the insulating films, and a step of forming a gate electrode on the gate insulating film, and the step of forming the gate insulating film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the gate insulating film consisting of a single-crystalline film.
According to a fiftieth aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprises a step of forming a plurality of second substrates, which are separated from each other through insulating films, in parallel above a first substrate, a step of forming first and second diffusion regions, which are separated from each other through active regions, on upper layer portions of the second substrates, a step of forming a gate insulating film over upper surfaces of a plurality of active regions, the first and second diffusion regions and the insulating films, and a step of forming a gate electrode on the gate insulating film, and the step of forming the first and second diffusion regions includes a step of previously forming amorphous or polycrystalline films and applying beams from directions which are perpendicular to densest crystal planes of plural different directions of the amorphous or polycrystalline films under a low temperature below a crystallization temperature thereby forming the active regions and the first and second diffusion regions consisting of single-crystalline films.
According to a fifty-first aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprises a step of forming a plurality of second substrates, which are separated from each other through insulating films, in parallel above a first substrate, a step of forming first and second diffusion regions, which are separated from each other through active regions, on upper layer portions of the second substrates, a step of forming a gate insulating film over upper surfaces of a plurality of active regions, the first and second diffusion regions and the insulating films, and a step of forming a gate electrode on the gate insulating film, and the step of forming the first and second diffusion regions includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the active regions and the first and second diffusion regions consisting of single-crystalline films.
According to the fiftieth or fifty-first aspect of the present invention, the step of forming the active regions and the first and second diffusion regions consisting of single-crystalline films preferably includes a step of forming substrate electrodes which are in contact with the second substrates, and the substrate electrodes are preferably single-crystallized simultaneously with single crystallization of the active regions and the first and second diffusion regions in the step of forming the substrate electrodes.
According to an fifty-second aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprising a plurality of memory cells comprises a step of alternately forming a plurality of diffusion and active regions above a semiconductor substrate, a step of forming a gate insulating film over upper surfaces of the plurality of diffusion and active regions, and a step of forming a gate electrode on an upper surface of the gate insulating film, and the step of forming the gate insulating film includes a step of previously forming an amorphous or polycrystalline film and applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions of the amorphous or polycrystalline thin film under a low temperature below a crystallization temperature thereby forming the gate insulating film consisting of a single-crystalline film.
According to a fifty-third aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprising a plurality of memory cells comprises a step of alternately forming a plurality of diffusion and active regions above a semiconductor substrate, a step of forming a gate insulating film over upper surfaces of the plurality of diffusion and active regions, and a step of forming a gate electrode on an upper surface of the gate insulating film, and the step of forming the gate insulating film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the gate insulating film consisting of a single-crystalline film.
According to a fifty-fourth aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprising a plurality of memory cells comprises a step of alternately forming a plurality of diffusion and active regions above a semiconductor substrate, a step of forming a gate insulating film over upper surfaces of the plurality of diffusion and active regions, and a step of forming a gate electrode on an upper surface of the gate insulating film, and the step of alternately forming the diffusion and active regions includes a step of previously forming amorphous or polycrystalline films and applying beams from directions which are perpendicular to densest crystal planes of plural of different directions of the amorphous or polycrystalline films under a low temperature below a crystallization temperature thereby forming the diffusion and active regions consisting of single-crystalline films.
According to a fifty-fifth aspect of the present invention, a method of fabricating a semiconductor device which is a nonvolatile electrically writable/erasable memory device comprising a plurality of memory cells comprises a step of alternately forming a plurality of diffusion and active regions above a semiconductor substrate, a step of forming a gate insulating film over upper surfaces of the plurality of diffusion and active regions, and a step of forming a gate electrode on an upper surface of the gate insulating film, and the step of alternately forming the diffusion and active regions includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions thereby forming the diffusion and active regions consisting of single-crystalline films.
According to the thirty-fifth, forty-second or forty-third aspect of the present invention, the dielectric film is formed by a single-crystalline film, whereby polarization field characteristics with respect to an external electric field are remarkably improved. Further, it is possible to maintain stability of the characteristics while attaining reduction in thickness.
According to the thirty-sixth, forty-fourth or forty-fifth aspect of the present invention, the floating gate is formed by a single-crystalline film, whereby a dense film having excellent crystallinity can be formed in formation of the second insulating film on the floating gate. Further, it is possible to prevent irregularization of the film surface by single-crystallizing the floating gate, thereby preventing reduction in withstand voltage of the interlayer film. Further, it is possible to improve electric properties of the memory device while attaining reduction in thickness.
According to the thirty-seventh, forty-sixth or forty-seventh aspect of the present invention, the second insulating film which is provided between the floating gate and the control gate is formed by a single-crystalline film of a high dielectric substance, whereby a large read current can be attained and data can be written in high efficiency even if an overlap area between the floating gate and the control gate is equalized to that of the channel region.
According to any of the thirty-fifth to forty-seventh aspects of the present invention, it is possible to easily form a single-crystalline film having a regulated crystal orientation with a freely set thickness on an upper surface of an underlayer, even if the underlayer has no single-crystalline structure.
According to the thirty-eighth, fortieth, forty-eighth, fifty-second or fifty-third aspect of the present invention, the gate insulating film of a ferroelectric substance is formed by a single-crystalline film, whereby polarization field characteristics with respect to an external electric field are remarkably improved in data rewriting or the like. Further, it is possible to maintain stability of the characteristics while attaining reduction in thickness. In addition, it is possible to minimize film fatigue of the gate insulating film since the crystalline structure is dense with a small amount of defects.
According to the thirty-ninth, forty-first, fiftieth, fifty-first, fifty-fourth or fifty-fifth aspect of the present invention, the active regions and the like are formed by single-crystalline films, whereby electron mobility is improved in the active regions to attain low resistance, thereby increasing the speed in write processing or the like. Further, it is possible to prevent occurrence of a leakage current in a gate-off state, due to a small amount of crystal defects in the diffusion and active regions. Thus, it is possible to increase a drain current ratio between gate-on and gate-off states, thereby remarkably improving electric properties of the semiconductor device.
According to the thirty-eight or thirty-ninth aspect of the present invention, it is possible to prevent deterioration with age by increasing denseness of crystals in the substrate electrode.
According to any of the thirty-eighth to fifty-fifth aspects of the present invention, no single-crystalline layer is required as an underlayer for serving as a seed crystal when the gate insulating film is formed by a single-crystalline film as in the thirty-eighth aspect or the diffusion and active regions are formed by single-crystalline films as in the thirty-ninth aspect, whereby it is possible to easily form a single-crystalline film having a regulated crystal orientation on any underlayer with a freely set thickness under a low temperature. After a plurality of second substrates which are isolated from each other through clearances and insulating films are grown/formed on the upper surface of the first substrate particularly as in the thirty-eighth or thirty-ninth aspect, it is possible to easily form single-crystalline films on upper layer portions or upper surfaces of the second substrates. Thus, it is possible to minimize clearances between the adjacent ones of the second substrates, thereby improving the degree of integration of the cell array.
Accordingly, an object of the present invention is to provide a semiconductor device which can increase remanence and maintain a high dielectric constant while maintaining a small cell size, and which can prevent a leakage current and improve durability, and a method of fabricating the same.
Another object of the present invention is to provide a semiconductor device which can read, write or erase data at a high speed without changing film thickness and cell size, and a method of fabricating the same.
Still another object of the present invention is to provide a semiconductor device which can attain improvement in crystallinity and densification of quality of respective layers and ensure withstands voltage by flattening film surfaces, and a method of fabricating the same.
A further object of the present invention is to provide an electrically writable/erasable semiconductor memory device which can implement a high degree of integration or mass storage by forming a 1-bit memory cell by only a single transistor part, and which can suppress fatigue of a gate oxide film.
A further object of the present invention is to provide an electrically writable/erasable semiconductor memory device which can increase remanence and maintain a high dielectric constant while maintaining a small cell size.
According to a fifty-sixth aspect of the present invention, a semiconductor device has a field-effect thin-film transistor on an upper surface of a substrate, and the field-effect thin-film transistor comprises a gate which is formed at least on a part of an upper side of the substrate, an insulating film which is formed on an upper surface (lower surface) of the gate, and a source and a drain which are selectively formed on an upper surface (lower surface) of the insulating film, while the gate, the source and the drain are formed by single-crystalline films.
Preferably, the semiconductor device further comprises a wiring film which is connected to at least any one of the gate, the source and the drain, and the wiring film is formed by a single-crystalline film.
According to a fifty-seventh aspect of the present invention, a semiconductor device has a field-effect thin-film transistor on an upper surface of a substrate, and the field-effect thin-film transistor comprises a gate which is formed at least on a part of an upper side of the substrate, a gate insulating film which is formed on an upper surface of the gate, and a source and a drain which are selectively formed on an upper surface of the gate insulating film respectively, while the gate insulating film is formed by a single-crystalline film.
According to a fifty-eighth aspect of the present invention, a semiconductor device has a field-effect thin-film transistor on an upper surface of a substrate, and the field-effect thin-film transistor comprises a gate which is formed at least on a part of an upper side of the substrate, a gate insulating film which is formed on an upper surface of the gate, a source and a drain which are formed on an upper surface of the gate insulating film to be separated from each other, and a channel which is interposed between the source and the drain, while the channel is formed by a single-crystalline film.
According to a fifty-ninth aspect of the present invention, a semiconductor device has a field-effect thin-film transistor and a condensed capacitance part which is arranged to be adjacent to the field-effect thin-film transistor on an upper surface of a substrate, and the field-effect thin-film transistor comprises a gate which is formed on a part of the upper surface of the substrate, a gate insulating film which is formed on an upper surface of the gate, and a source and a drain which are formed on an upper surface of the gate insulating film to be separated from each other, while the condensed capacitance part comprises a lower electrode which is formed on a part of the upper surface of the substrate, a dielectric film which is formed on an upper surface of the lower electrode, and an upper electrode which is formed on an upper surface of the dielectric film. The gate of the field-effect thin-film transistor and the lower electrode of the condensed capacitance part are formed by single-crystalline films.
Preferably, the dielectric film of the condensed capacitance part and the gate insulating film of the field-effect thin-film transistor are formed by single-crystalline films of high dielectric or ferroelectric substances.
According to any of the fifty-sixth to fifty-ninth aspects of the present invention, each single-crystalline film is preferably formed by supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions.
According to any of the fifty-sixth to fifty-ninth aspects of the present invention, each single-crystalline film is preferably formed by applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions under a low temperature below a crystallization temperature of a previously formed amorphous or polycrystalline thin film.
The present invention is also directed to a method of fabricating a semiconductor device. According to a sixtieth aspect of the present invention, a method of fabricating a semiconductor device having a field-effect thin-film transistor comprises a step of forming a gate at least on a part of an upper side of a substrate, a step of forming a gate insulating film on an upper surface of the gate, and a step of selectively forming a source and a drain on an upper surface of the gate insulating film, and the steps of forming the gate, the source and the drain include steps of supplying reaction gases under low temperatures below crystallization temperatures and simultaneously applying beams from directions which are perpendicular to densest crystal planes of plural different directions for forming the gate, the source and the drain consisting of single-crystalline films.
According to a sixty-first aspect of the present invention, a method of fabricating a semiconductor device having a field-effect thin-film transistor comprises a step of forming a gate at least on a part of an upper side of a substrate, a step of forming a gate insulating film on an upper surface (lower surface) of the gate, and a step of selectively forming a source and a drain on an upper surface (lower surface) of the gate insulating film, and the steps of forming the gate, the source and the drain include steps of previously forming amorphous or polycrystalline thin films and applying beams from directions which are perpendicular to densest crystal planes of plural different directions under low temperatures below crystallization temperatures for forming the gate, the source and the drain consisting of single-crystalline films.
According to a sixty-second aspect of the present invention, a method of fabricating a semiconductor device having a field-effect thin-film transistor and a condensed capacitance part comprises a step of forming a lower electrode for condensed capacitance and a gate for the transistor on a surface of a substrate, a step of forming a dielectric film on an upper surface of the lower electrode for condensed capacitance, a step of selectively forming an upper electrode for condensed capacitance on an upper surface of the dielectric film, a step of forming a gate insulating film on an upper surface of the gate for the transistor, and a step of forming a source and a drain on an upper surface side of the gate insulating film, and the step of forming the dielectric film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a plurality of different directions for forming the dielectric film consisting of a single-crystalline film.
According to a sixty-third aspect of the present invention, a method of fabricating a semiconductor device having a field-effect thin-film transistor and a condensed capacitance part comprises a step of forming a lower electrode for condensed capacitance and a gate for the transistor on a surface of a substrate, a step of forming a dielectric film on an upper surface of the lower electrode for condensed capacitance, a step of selectively forming an upper electrode for condensed capacitance on an upper surface of the dielectric film, a step of forming a gate insulating film on an upper surface of the gate for the transistor, and a step of forming a source and a drain on an upper surface side of the gate insulating film, and the steps of forming the dielectric film and the gate insulating film include steps of previously forming amorphous or polycrystalline thin films and applying beams from directions which are perpendicular to densest crystal planes of plural different directions under low temperatures below crystallization temperatures for forming the dielectric film and the gate insulating film consisting of single-crystalline films.
According to a sixty-fourth aspect of the present invention, a method of fabricating a semiconductor device having a field-effect thin-film transistor and a condensed capacitance part comprises a step of forming a lower electrode for condensed capacitance and a gate for the transistor on a surface of a substrate, a step of forming a dielectric film on an upper surface of the lower electrode for condensed capacitance, a step of selectively forming an upper electrode for condensed capacitance on an upper surface of the dielectric film, a step of forming a gate insulating film on an upper surface of the gate for the transistor, a step of forming a channel on an upper surface of the gate insulating film, and a step of forming a source and a drain on both sides of the channel, and the steps of forming the channel, the source and the drain include steps of supplying reaction gases under low temperatures below crystallization temperatures and simultaneously applying beams from directions which are perpendicular to densest crystal planes of plural different directions for forming the channel, the source and the drain consisting of single-crystalline films.
According to a sixty-fifth aspect of the present invention, a method of fabricating a semiconductor device having a field-effect thin-film transistor and a condensed capacitance part comprises a step of forming a lower electrode for condensed capacitance and a gate for the transistor on a surface of a substrate, a step of forming a dielectric film on an upper surface of the lower electrode for condensed capacitance, a step of selectively forming an upper electrode for condensed capacitance on an upper surface of the dielectric film, a step of forming a gate insulating film on an upper surface of the gate for the transistor, a step of forming a channel on an upper surface of the gate insulating film, and a step of forming a source and a drain on both sides of the channel, and the steps of forming the channel, the source and the drain include steps of previously forming amorphous or polycrystalline thin films and applying beams from directions which are perpendicular to densest crystal planes of plural different directions under low temperatures below crystallization temperatures for forming the channel, the source and the drain consisting of single-crystalline films.
According to the fifty-sixth, sixtieth or sixty-first aspect of the present invention, the gate, the source and the drain and the wiring film which is connected to at least any one of the same are formed by single-crystalline films. When these films are formed by silicon single-crystalline films and the gate insulating film is formed by a thermal oxide film of the single-crystalline silicon forming the gate, or the source and the drain, therefore, it is possible to attain thickness reduction while maintaining excellent insulativity for increasing an ON-state current of the transistor as compared with a case of forming the same by a thermal oxide film of a polycrystalline or amorphous film. Since the source and the drain are formed by single-crystalline films, further, it is possible to remarkably reduce a source-to-drain leakage current as compared with a case of forming the same by polycrystalline or amorphous films. Since the gate, the source, the drain and the wiring film are formed by single-crystalline films, in addition, insulativity is improved when interlayer insulating films between these layers are formed by thermal oxide films of these films as compared with a case of forming the same by thermal oxide films of polycrystalline or amorphous films. Therefore, a high-speed operation is enabled by increasing the ON-state current and reducing a time for charging condensed capacitance immediately after writing, while it is possible to reduce a standby current by reducing the OFF-state current.
According to the fifty-seventh aspect of the present invention, the gate insulating film is formed by a single-crystalline film, whereby it is possible to reduce its thickness while ensuring its withstand voltage. Thus, it is possible to remarkably reduce the formation area, thereby reducing the cell area of the overall field-effect thin-film transistor and improving its numerical aperture.
According to the fifty-eighth aspect of the present invention, the channel is formed by a single-crystalline film, whereby electron mobility in the channel is improved for attaining low resistance in an ON state of the transistor and high-speed processing of the semiconductor device is enabled. In an OFF state, on the other hand, crystal defects are remarkably reduced as compared with a polycrystalline or amorphous film, whereby occurrence of a leakage current can be prevented. Thus, it is possible to increase the ratio of a drain current in an ON state to that in an OFF state, thereby remarkably improving electrical properties.
According to any of the fifty-ninth, sixty-fourth and sixty-fifth aspects of the present invention, the gate of the field-effect thin-film transistor and the lower electrode of the condensed capacitance part are formed by single-crystalline films, whereby growth of hillocks, which are observed in polycrystalline or amorphous films, is hardly caused when Al is employed as the material, for example. Therefore, it is possible to remarkably reduce the thickness of the gate insulating film of the transistor which is formed on the gate and the lower electrode of the condensed capacitance part or the dielectric film of the condensed capacitance part as compared with the prior art, to increase the ON-state current of the transistor and to reduce the area of the condensed capacitance part, whereby high-speed processing as well as miniaturization are enabled.
According to any of the fifty-ninth, sixty-second and sixty-third aspects of the present invention, the dielectric film of the condensed capacitance part is formed by a single-crystalline film of a high dielectric or ferroelectric substance, whereby the dielectric film can be reduced in thickness and it is possible to remarkably reduce its formation area while stably ensuring sufficient capacitance. Thus, it is possible to reduce the cell area of the overall condensed capacitance part for improving its numerical aperture.
According to any of the fifty-sixth to sixty-fifth aspects of the present invention, it is possible to easily form a single-crystalline film having a regularized crystal orientation on an upper surface of each underlayer with setting of a free film thickness under a low temperature, even if the underlayer is not in a single-crystalline structure.
According to each of the fifty-sixth, sixtieth and sixty-first aspects of the present invention, the gate, the source and the drain and the wiring film which is connected to at least one of the same are formed by single-crystalline films, whereby high electron mobility is attained. Thus, it is possible to increase the ratio of a drain current in an ON state of the transistor to that in an OFF state as compared with a case of forming the same by polycrystalline or amorphous films. Therefore, a high-speed operation is enabled by increasing the ON-state current and reducing a time for charging condensed capacitance immediately after writing, while it is possible to reduce an OFF-state current for reducing a standby current.
According to the fifty-seventh aspect of the present invention, the gate insulating film is formed by a single-crystalline film, whereby it is possible to reduce its thickness while ensuring its withstand voltage, to remarkably reduce its formation area and to reduce the cell area of the overall field-effect thin-film transistor for improving its numerical aperture.
According to the fifty-eighth aspect of the present invention, the channel is formed by a single-crystalline film, whereby electron mobility in the channel is improved for attaining low resistance in an ON state of the transistor thereby enabling high-speed processing of the semiconductor device. In an OFF state, on the other hand, crystal defects are remarkably reduced as compared with a polycrystalline or amorphous film, whereby occurrence of a leakage current can be prevented. Thus, it is possible to increase the ratio of a drain current in an ON state to that in an OFF state, thereby remarkably improving electrical properties.
According to any of the fifty-ninth, sixty-fourth and sixty-fifth aspects of the present invention, the gate of the field-effect thin-film transistor and the lower electrode of the condensed capacitance part are formed by single-crystalline films, whereby it is possible to remarkably reduce the thicknesses of the dielectric film of the condensed capacitance part and the gate insulating film of the transistor formed thereon for increasing driving force of the condensed capacitance part and the transistor, whereby high-speed processing is enabled also upon miniaturization.
According to any of the fifty-ninth, sixty-second and sixty-third aspects of the present invention, the dielectric film of the condensed capacitance part is formed by a single-crystalline film of a high dielectric or ferroelectric substance, whereby it is possible to remarkably reduce its formation area while stably ensuring sufficient capacitance for implementing reduction in thickness of the dielectric film. Thus, it is possible to reduce the cell area of the overall condensed capacitance part for improving its numerical aperture.
According to any of the fifty-sixth to sixty-fifth aspects of the present invention, it is possible to easily form a single-crystalline film having a regularized crystal orientation on an upper surface of each underlayer with setting of a free film thickness under a low temperature, even if the underlayer is not in a single-crystalline structure. According to such a forming method, further, no influence is exerted by a step when the shape of the substrate is substantially at the same degree as that of an ordinary semiconductor device.
Accordingly, an object of the present invention is to provide a semiconductor device having a large ON-state current and a small OFF-state current and a method of fabricating the same.
Another object of the present invention is to provide a semiconductor device which can implement improvement in definition and a method of fabricating the same.
Still another object of the present invention is to provide a semiconductor device which can attain increase in operating speed and a method of fabricating the same.
A further object of the present invention is to provide a semiconductor device which can prevent occurrence of hillocks for omitting a step of forming Al2O3 layers and a method of fabricating the same.
According to a sixty-sixth aspect of the present invention, a liquid crystal display comprises an electrically insulating transparent substrate which is provided thereon with a pixel electrode of a liquid crystal element and a thin-film transistor for driving the liquid crystal element, and the transparent substrate is substantially made of a material having a withstand temperature of not more than 600xc2x0 C., while an active layer of the thin-film transistor is substantially formed by a crystalline semiconductor thin film having carrier mobility exceeding 10 cm2/(V.sec.).
Preferably, a control electrode in the thin-film transistor is substantially formed by a crystalline semiconductor thin film.
Preferably, a driving circuit for driving the thin-film transistor is further formed on the transparent substrate.
The present invention is also directed to a method of fabricating a liquid crystal display. According to a sixty-seventh aspect of the present invention, the method of fabricating a liquid crystal display comprising an electrically insulating transparent substrate which is provided thereon with a pixel electrode of a liquid crystal element and a thin-film transistor, having an active layer substantially formed by a crystalline semiconductor thin film, for driving the liquid crystal element, comprises (a) a step of preparing an electrically insulating transparent substrate having a withstand temperature of not more than 600xc2x0 C., (b) a step of forming an amorphous semiconductor thin film on the transparent substrate, (c) a step of irradiating a surface of the semiconductor thin film with a gas beam of low energy causing no sputtering of the semiconductor thin film from a prescribed direction during or after the step (b), thereby converting the semiconductor thin film to a crystalline semiconductor thin film, and (d) a step of introducing a prescribed impurity into the crystalline semiconductor thin film which is formed in the step (c), thereby forming the active layer.
Preferably, the prescribed direction in the step (c) is a plurality of directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline body of the semiconductor thin film having a constant crystal orientation.
Preferably, the method of fabricating a liquid crystal display further comprises (e) a step of forming an insulating film on the crystalline semiconductor thin film which is formed in the step (c), (f) a step of regarding the semiconductor thin film as a first semiconductor thin film and forming an amorphous second semiconductor thin film on the insulating film, (g) a step of irradiating a surface of the second semiconductor thin film with a gas beam of low energy causing no sputtering of the second semiconductor thin film from a prescribed direction during or after the step (f), thereby converting the second semiconductor thin film to a crystalline semiconductor thin film, and (h) a step of selectively removing the second semiconductor thin film after the step (f), thereby molding the same into a shape of a control electrode of the thin-film transistor, and a prescribed impurity is introduced into the first semiconductor thin film through the control electrode serving as a screen in the step (d), thereby forming the active layer.
Preferably, the step (h) comprises (h-1) a step of forming a screen film on the second semiconductor layer by photolithography, and (h-2) a step of etching the second semiconductor layer thereby selectively forming the control electrode under the screen film, and the prescribed direction in the step (g) is a plurality of directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline body of the semiconductor thin film having a constant crystal orientation.
Preferably, the method of fabricating a liquid crystal display further comprises (i) a step of forming a driving circuit for driving the thin-film transistor on the transparent substrate, and the step (i) comprises (i-1) a step of regarding the semiconductor thin film as a first semiconductor thin film and forming an amorphous second semiconductor thin film of the same material as the first semiconductor thin film on the transparent substrate simultaneously with the step (b), (i-2) a step of irradiating a surface of the second semiconductor thin film with a gas beam of low energy causing no sputtering of the second semiconductor thin film from the prescribed direction simultaneously with the step (c), thereby converting the second semiconductor thin film to a crystalline semiconductor thin film, and (i-3) a step of introducing a prescribed impurity into the crystalline semiconductor thin film which is formed in the step (i-2), thereby forming an active layer of a circuit element forming the driving circuit.
Preferably, the method of fabricating a liquid crystal display further comprises (j) a step of forming a driving circuit for driving the thin-film transistor on the transparent substrate, and the step (j) comprises (j-1) a step of forming an amorphous third semiconductor thin film of the same material as the first semiconductor thin film on the transparent substrate simultaneously with the step (b), (i-2) a step of irradiating a surface of the, third semiconductor thin film with gas beams of low energy causing no sputtering of the third semiconductor thin film from the prescribed direction in the step (c) simultaneously with the step (c), thereby converting the third semiconductor thin film to a crystalline semiconductor thin film, (j-3) a step of regarding the insulating film as a first insulating film and forming a second insulating film of the same material as the first insulating film of the same material as the first insulating film on the crystalline semiconductor thin film simultaneously with the step (e), (j-4) a step of forming an amorphous fourth semiconductor thin film of the same material as the second semiconductor thin film on the second insulating film simultaneously with the step (f), (j-5) a step of irradiating a surface of the fourth semiconductor thin film with a gas beam of low energy causing no sputtering of the fourth semiconductor thin film from the prescribed direction in the step (g), thereby converting the fourth semiconductor thin film to a crystalline semiconductor thin film, (j-6) a step of selectively removing the fourth semiconductor thin film simultaneously with the step (h), thereby molding the same into the shape of a control electrode in the circuit element, and (j-7) a step of introducing a prescribed impurity into the third semiconductor thin film through the control electrode serving as a screen, thereby forming an active layer of a circuit element forming the driving circuit.
In the liquid crystal display according to the sixty-sixth aspect of the present invention, the transparent substrate is substantially made of a material having a withstand temperature of not more than 600xc2x0 C., whereby the unit can be formed with a low-priced transparent substrate. In other words, it is possible to form the liquid crystal display at a low cost. Further, the active layer of the thin-film transistor is substantially formed by a crystalline semiconductor thin film having high carrier mobility, whereby the thin-film transistor has a large ON-state current. Thus, it is possible to display an image having high contrast with small flicker noise. Further, it is possible to refine the thin-film transistor due to the large ON-state current, whereby a high-definition image can be displayed.
According to the sixty-sixth aspect of the present invention, the control electrode is substantially formed by a crystalline thin film, whereby the active layer can be formed by a self-alignment technique. Thus, the thin-film transistor can be refined, whereby it is possible to display an image in higher definition.
According to the sixty-sixth aspect of the present invention, the driving circuit is formed on the same transparent substrate as that for the thin-film transistor and the pixel electrode of the liquid crystal element, whereby it is possible to display an image without setting a driving circuit in the exterior. In other words, it is possible to easily utilize the liquid crystal display at a low cost.
In the method of fabricating a liquid crystal display according to the sixty-seventh aspect of the present invention, the gas beam of low energy causing no sputtering of the target substance is applied from a prescribed direction after or while an amorphous semiconductor thin film is formed on the transparent substrate, leading to action of the so-called law of Bravais. In other words, the thin film as irradiated is converted to a crystal having such a crystal orientation that a plane perpendicular to the direction of irradiation defines the densest crystal plane. Thus, a crystalline semiconductor thin film forming an active layer of the thin-film transistor is formed on the transparent substrate. Due to irradiation with the gas beam, further, it is possible to form a crystalline active layer on the transparent substrate having a withstand temperature of not more than 600xc2x0 C. Thus, it is possible to fabricate a liquid crystal display for displaying a high-quality image at a low cost according to this method.
According to the sixty-seventh aspect of the present invention, the gas beams are applied from a plurality of directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline body having a constant crystal orientation, whereby the semiconductor thin film forming the active layer is set only in a single crystal orientation. Namely, a single-crystalline active layer having a regularized crystal orientation is formed on the transparent substrate. Thus, carrier mobility in the active layer is further improved as compared with a polycrystalline active layer. Further, it is possible to form a single-crystalline active layer on the transparent substrate having a withstand temperature of not more than 600xc2x0 C., due to the irradiation with gas beams. According to this method, it is possible to fabricate a liquid crystal display for displaying an image of higher quality at a low cost. Further, it is also possible to fabricate a transmission type liquid crystal display since the active layer is formed as a thin film which is single-crystalline.
According to the sixty-seventh aspect of the present invention, the gas beam of low energy causing no sputtering is applied from a prescribed direction after or while an amorphous semiconductor thin film is formed on the insulating film. Therefore, the target thin film as irradiated is converted to a crystal having such a crystal orientation that planes perpendicular to the directions of irradiation define densest crystal planes. Thus, a crystalline semiconductor thin film forming a control electrode of the thin-film transistor is formed on the insulating film. Due to the irradiation with the gas beam, further, it is possible to form the crystalline control electrode without heating the transparent substrate having a withstand temperature of not more than 600xc2x0 C. in excess of the withstand temperature. Further, the active layer is formed in a self-alignment manner by introduction of an impurity through the crystalline control electrode serving as a screen. Thus, it is possible to refine the thin-film transistor, whereby a liquid crystal display for displaying an image of higher definition can be fabricated at a low cost.
According to the sixty-seventh aspect of the present invention, the gas beams are applied from a plurality of directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline body having a constant crystal orientation, whereby the semiconductor thin film formed on the insulating film is set only in a single crystal orientation. Namely, the second semiconductor thin film is formed as a single crystal having a regulated crystal orientation. Thus, it is possible to easily form a screen film on the second semiconductor thin film by photolithography, since no light is irregularly reflected from the second semiconductor thin film. Further, etching of the semiconductor thin film can be easily controlled due to uniform progress of the etching. In addition, it is possible to easily form a uniform compound film with a metal having a high melting point, for example, on the second semiconductor thin film. According to this method, fabrication steps are simplified and the liquid crystal display as fabricated is improved in reliability.
According to the sixty-seventh aspect of the present invention, it is possible to fabricate such a liquid crystal display that a driving circuit is formed on the same transparent substrate as that for the thin-film transistor and the pixel electrode of the liquid crystal element. Namely, it is possible to easily fabricate a liquid crystal display at a low cost. Further, efficiency of fabrication is improved since the active layer of the thin-film transistor and that of a circuit element forming the driving circuit are simultaneously formed and the control electrode of the thin-film transistor.
According to the sixty-seventh aspect of the present invention, it is possible to fabricate such a liquid crystal display that a driving circuit is formed on the same transparent substrate as that for the thin-film transistor and the pixel electrode of a liquid crystal element. Namely, it is possible to easily fabricate a liquid crystal display at a low cost. Further, efficiency of fabrication is improved since the active layer of the thin-film transistor and that of a circuit element forming the driving circuit are simultaneously formed while a control electrode of the thin-film transistor and that of the circuit element forming the driving circuit are also simultaneously formed.
In the liquid crystal display according to the sixty-sixth aspect of the present invention, the transparent substrate is substantially made of a material having a withstand temperature of not more than 600xc2x0 C., whereby the display can be formed at a low cost. Further, the active layer of the thin-film transistor is substantially formed by a crystalline semiconductor thin film having high carrier mobility, whereby it is possible to display a high-definition image having high contrast with small flicker noise.
According to the sixty-sixth aspect of the present invention, the control electrode of the thin-film transistor is substantially formed by a crystalline semiconductor thin film, whereby the active layer can be formed by a self-alignment technique. Thus, the thin-film transistor can be refined, whereby it is possible to display an image of higher definition.
According to the sixty-sixth aspect of the present invention, the driving circuit is formed on the same transparent substrate as that for the thin-film transistor and the pixel electrode of the liquid crystal element, whereby it is possible to display an image without setting a driving circuit in the exterior. In other words, it is possible to easily utilize the liquid crystal display at a low cost.
In the method of fabricating a liquid crystal display according to the sixty-seventh aspect of the present invention, the gas beam of low energy causing no sputtering of the target substance is applied from a prescribed direction after or while an amorphous semiconductor thin film is formed on the transparent substrate, whereby it is possible to form a crystalline active layer forming an active layer of the thin-film transistor on the transparent substrate having a withstand temperature of not more than 600xc2x0 C. Thus, it is possible to fabricate a liquid crystal display for displaying a high-quality image at a low cost.
According to the sixty-seventh aspect of the present invention, the gas beams are applied from a plurality of directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline body having a constant crystal orientation, whereby a single-crystalline semiconductor thin film having a regularized crystal orientation for forming the active layer of the thin-film transistor can be formed on the transparent substrate having a withstand temperature of not more than 600xc2x0 C. According to this method, it is possible to fabricate a liquid crystal display for displaying an image of higher quality at a low cost. Further, it is also possible to fabricate a transmission type liquid crystal display since the active layer is formed as a thin film which is single-crystalline.
According to the sixty-seventh aspect of the present invention, the gas beam of low energy causing no sputtering is applied from a prescribed direction after or while an amorphous semiconductor thin film is formed on the insulating film, whereby a crystalline semiconductor thin film forming a control electrode of the thin-film transistor can be formed on the insulating film without heating the transparent substrate having a withstand temperature of not more than 600xc2x0 C. in excess of the withstand temperature. Further, an active layer is formed in a self-alignment manner by introduction of an impurity through the crystalline control electrode serving as a screen. Thus, it is possible to refine the thin-film transistor, whereby a liquid crystal display for displaying an image of higher definition can be fabricated at a low cost.
According to the sixty-seventh aspect of the present invention, the gas beams are applied from a plurality of directions which are perpendicular to a plurality of densest crystal planes having different directions in a single-crystalline body having a constant crystal orientation, whereby the second semiconductor thin film is formed as a single crystal having a regulated crystal orientation without heating the transparent substrate having a withstand temperature of not more than 600xc2x0 C. in excess of the withstand temperature. Thus, it is possible to easily form a screen film on the second semiconductor thin film by photolithography. Further, etching of the semiconductor thin film can be easily controlled. In addition, it is possible to easily form a uniform compound film with a metal having a high melting point, for example, on the second semiconductor thin film. According to this method, fabrication steps are simplified and the liquid crystal display as fabricated is improved in reliability.
According to the sixty-seventh aspect of the present invention, it is possible to easily fabricate such a liquid crystal display that a driving circuit is formed on the same transparent substrate as that for the thin-film transistor and the pixel electrode of the liquid crystal element at a low cost. Further, efficiency of fabrication is improved since the active layer of the thin-film transistor and that of a circuit element forming the driving circuit are simultaneously formed.
According to the sixty-seventh aspect of the present invention, it is possible to easily fabricate such a liquid crystal display that a driving circuit is formed on the same transparent substrate as that for the thin-film transistor and the pixel electrode of the liquid crystal element, i.e., a liquid crystal display which can be easily utilized at a low cost. Further, efficiency of fabrication is further improved since the active layer of the thin-film transistor and that of the circuit element forming the driving circuit are simultaneously formed while a control electrode of the thin-film transistor and that of the circuit element forming the driving circuit are also simultaneously formed.
Accordingly, an object of the present invention is to provide a liquid crystal display which can be fabricated at a low cost for displaying an image of high quality, and a method of fabricating the same.
According to a sixty-eighth aspect of the present invention, an insulated gate semiconductor device comprises a semiconductor substrate, a source and a drain which are selectively formed on the semiconductor substrate, a channel which is formed between the source and the drain, a gate insulating film which is formed on an upper surface of the channel, and a gate which is formed on an upper surface of the gate insulating film, and the channel is formed by a single-crystalline film.
Preferably, the gate insulating film is prepared from a single-crystalline high dielectric film or a single-crystalline ferroelectric film.
Preferably, the single-crystalline film is formed by forming a single-crystalline thin film by supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions and thereafter growing a thick single-crystalline film on the single-crystalline thin film serving as a seed crystal.
Preferably, the single-crystalline film is formed by repeating a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions thereby growing a thick single-crystalline film.
According to a sixty-ninth aspect of the present invention, an insulated gate semiconductor device comprises a semiconductor device, a source and a drain which are selectively formed on the semiconductor substrate, a gate insulating film which is formed on a portion of the semiconductor substrate between the source and the drain, and a gate which is formed on an upper surface of the gate insulating film, and the gate insulating film is formed by a single-crystalline film.
According to a seventieth aspect of the present invention, an insulated gate semiconductor device comprises a semiconductor substrate, a source and a drain which are selectively formed on the semiconductor substrate, a gate insulating film which is formed on a portion of the semiconductor substrate between the source and the drain, and a gate which is formed on an upper surface of the gate insulating film, and the source and the drain are formed by single-crystalline films.
According to a seventy-first aspect of the present invention, an insulated gate semiconductor device comprises a semiconductor substrate, a source and a drain which are selectively formed on the semiconductor substrate, a gate insulating film which is formed on a portion of the semiconductor substrate between the source and the drain, a gate which is formed on an upper surface of the gate insulating film, a first insulating film which is formed on an upper surface of the gate, an interconnection layer which is formed on an upper surface of each of the source and the drain or over an upper surface of the gate and a part of an upper surface of the first insulating film, a second insulating film which is formed on upper surfaces of the interconnection film and the first insulating film, and a flattening film for an etchback operation which is formed on an upper surface of the second insulating film, and a contact hole is formed through an upper surface of the flattening film and the second insulating film to reach the upper surface of the interconnection film, while the flattening film and the second insulating film are formed by single-crystalline films having substantially equal degrees of crystallinity.
According to a seventy-second aspect of the present invention, a bipolar semiconductor device comprises a semiconductor substrate, and a multilayer semiconductor layer which is formed on an upper surface of the semiconductor substrate and including a collector, a base and an emitter, and at least one of the collector, the base and the emitter is formed by a single-crystalline film.
According to the sixty-eighth, sixty-ninth, seventieth, seventy-first or seventy-second aspect of the present invention, the single-crystalline film is preferably formed by supplying a reaction gas under a low temperature below a crystalline temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions.
According to the sixty-eighth, sixty-ninth, seventieth, seventy-first or seventy-second aspect of the present invention, the single-crystalline film is preferably formed by applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions under a low temperature below a crystallization temperature of a previously formed amorphous or polycrystalline thin film.
The present invention is also directed to a method of fabricating an insulated gate semiconductor device. According to a seventy-third aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of forming a channel on an upper surface of a semiconductor substrate between regions for defining a source and a drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the channel includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions thereby forming the channel of a single-crystalline film.
According to a seventy-fourth aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of forming a channel on an upper surface of a semiconductor substrate between regions for defining a source and a drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the channel includes a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions under a low temperature below a crystallization temperature thereby forming the channel of a single-crystalline film.
According to the seventy-third or seventy-fourth aspect of the present invention, the single-crystalline film is preferably formed to also include the regions for defining the source and the drain in the step of forming the channel, and an impurity is preferably introduced into the regions for defining the source and the drain through a mask of the gate after the step of forming the gate.
According to an seventy-fifth aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of selectively forming a source and a drain on an upper surface of a semiconductor device for forming a channel between the source and the drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the gate insulating film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions thereby forming the gate insulating film of a single-crystalline film.
According to a seventy-sixth aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of selectively forming a source and a drain on an upper surface of a semiconductor device for forming a channel between the source and the drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the gate insulating film includes a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions under a low temperature below a crystallization temperature thereby forming the gate insulating film of a single-crystalline film.
According to a seventy-seventh aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of forming a channel on an upper surface of a semiconductor substrate between regions for defining a source and a drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the channel includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions thereby forming the regions for defining the source and the drain of single-crystalline films.
According to an seventy-eighth aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of forming a channel on an upper surface of a semiconductor substrate between regions for defining a source and a drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the channel includes a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions under a low temperature below a crystallization temperature thereby forming the regions for defining the source and the drain of single-crystalline films.
According to the seventy-seventh or seventy-eighth aspect of the present invention, the single-crystalline films are preferably formed to also include a region for defining the channel in the step of forming the channel, and an impurity is preferably introduced into the regions for defining the source and the drain through a mask of the gate after the step of forming the gate.
According to a seventy-ninth aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of selectively forming a source and a drain on an upper surface of a semiconductor substrate, a step of forming a gate insulating film on a portion of the semiconductor substrate between the source and the drain, a step of forming a gate on an upper surface of the gate insulating film, a step of forming a first insulating film on an upper surface of the gate, a step of forming an interconnection film on an upper surface of each of the source and the drain or over an upper surface of the gate and a part of an upper surface of the first insulating film, a step of forming a second insulating film on upper surfaces of the interconnection film and the first insulating film, a step of forming a flattening film for an etchback operation on an upper surface of the second insulating film and a step of forming a contact hole through an upper surface of the flattening film and the second insulating film to reach the upper surface of the interconnection film, and each of the steps of forming the flattening film and the second insulating film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest planes of a single direction or a plurality of different directions for forming each of the flattening film and the second insulating film of single-crystalline films having substantially equal degrees of crystallinity.
According to an eightieth aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of selectively forming a source and a drain on an upper surface of a semiconductor substrate, a step of forming a gate insulating film on a portion of the semiconductor substrate between the source and the drain, a step of forming a gate on an upper surface of the gate insulating film, a step of forming a first insulating film on an upper surface of the gate, a step of forming an interconnection film on an upper surface of each of the source and the drain or over an upper surface of the gate and a part of an upper surface of the first insulating film, a step of forming a second insulating film on upper surfaces of the interconnection film and the first insulating film, a step of forming a flattening film for an etchback operation on an upper surface of the second insulating film, and a step of forming a contact hole through an upper surface of the flattening film and the second insulating film to reach the upper surface of the interconnection film, and each of the steps of forming the flattening film and the second insulating film includes a step of previously forming an amorphous or polycrystalline thin film and applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions under a low temperature below a crystallization temperature for forming each of the flattening film and the second insulating film of single-crystalline films having substantially equal degrees of crystallinity.
According to an eighty-first aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of selectively forming a source and a drain on an upper surface of a semiconductor substrate for forming a channel between the source and the drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the gate insulating film includes a step of supplying a reaction gas under a low temperature below a crystallization temperature and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions for forming a single-crystalline thin film, and thereafter growing a thick single-crystalline film on the single-crystalline thin film serving as a seed crystal thereby forming the gate insulating film.
According to an eighty-second aspect of the present invention, a method of fabricating an insulated gate semiconductor device comprises a step of selectively forming a source and a drain on an upper surface of a semiconductor substrate for forming a channel between the source and the drain, a step of forming a gate insulating film on an upper surface of the channel, and a step of forming a gate on an upper surface of the gate insulating film, and the step of forming the gate insulating film includes a step of growing a thick single-crystalline film by repeating a step of supplying a reaction gas under a low temperature below a crystallization temperature. and simultaneously applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions for forming a single-crystalline thin film thereby forming the gate insulating film.
According to an eighty-third aspect of the present invention, a method of fabricating a bipolar semiconductor device comprises a plurality of formation steps of forming respective formation layers of a collector, a base and an emitter in which impurities are introduced respectively on an upper surface of a semiconductor substrate respectively, and a plurality of activation steps of activating the formation layers after the respective formation steps, and one of the activation steps for activating at least one of the formation layers includes a step of applying beams from directions which are perpendicular to densest crystal planes of a single direction or a plurality of different directions under a low temperature allowing no impurity diffusion and supplying impacts to a number of particles in a target while simultaneously single-crystallizing the formation layer.
According to each of the sixty-eighth, seventy-third and seventy-fourth aspects of the present invention, the channel is formed by a single-crystalline film, whereby it is possible to improve electron mobility in the channel for reducing the resistance value when the transistor is turned on, and an OFF-state current can be reduced by preventing occurrence of a leakage current by a regular crystal structure when the transistor is turned off.
According to each of the sixty-eighth, seventy-fifth and seventy-sixth aspects of the present invention, the gate insulating film is formed by a single-crystalline film, whereby it is possible to prevent occurrence of a leakage current and to remarkably improve the insulating film withstand voltage.
According to each of the seventieth, seventy-seventh and seventy-eighth aspects of the present invention, the source and the drain are formed by single-crystalline films, whereby it is possible to prevent occurrence of a leakage current caused by crystal defects and to reduce an OFF-state current of the transistor.
According to each of the seventy-first, seventy-ninth and eightieth aspects of the present invention, the flattening film for an etchback operation and the second insulating film serving as an underlayer thereof have substantially equal degrees of crystallinity and the overall surfaces of the flattening film and the second insulating film serving as its underlayer are etched in this state to flatten the flattening film for serving as an underlayer for the second interconnection layer and thereafter a contact hole is formed through the upper surface of the flattening film and the second insulating film to reach the upper surface of the interconnection film, whereby the flattening film and the second insulating film are at the same etching rates in formation of the contact hole to facilitate the etching operation.
According to each of the sixty-eighth, eighty-first and eighty-second aspects of the present invention, the gate insulating film is formed by a single-crystalline high dielectric film or a single-crystalline ferroelectric film, whereby the same can be formed in a relatively large thickness and is remarkably improved in insulating property.
According to each of the seventy-second and eighty-third aspects of the present invention, at least one layer of the collector, the base and the emitter is formed by a single-crystalline film, whereby it is possible to improve electron mobility and reduce the resistance when the transistor is turned on, while occurrence of a leakage current can be prevented to suppress current consumption by regulating the crystal structure when the transistor is turned off. Namely, it is possible to provide a high characteristic semiconductor device having a high ON-OFF ratio of a collector current.
According to each of the sixty-eighth to eighty-second aspects of the embodiment, it is possible to easily form a single-crystalline thin film having a regulated crystal orientation on an arbitrary underlayer under a low temperature. According to each of the sixty-eighth, eighty-first and eighty-second aspects of the present invention, in particular, it is possible to form a homogeneous and stable single-crystalline film even if a constant thickness is required for the single-crystalline film.
According to the eighty-third aspect of the present invention, the formation layers can be activated with no high-temperature treatment and no impurity diffusion, whereby the thicknesses and activation characteristics of the respective formation layers can be accurately controlled to reduce characteristic dispersion of the semiconductor device. Further, at least one of the formation layers is so single-crystallized that electron mobility can be improved to reduce the resistance when the transistor is turned on while occurrence of a leakage current can be prevented to suppress current consumption by regulating the crystal structure when the transistor is turned off. Namely, it is possible to provide a high characteristic semiconductor device having a high ON-OFF ratio of a drain current.
According to each of the seventy-third, seventy-fourth, seventy-seventh and seventy-eighth aspects of the present invention, the regions for defining the source and the drain and the channel are simultaneously single-crystallized so that an impurity is introduced into the regions for defining the source and the drain through a mask of the gate, whereby it is possible to fabricate a semiconductor device having a single-crystalline structure in self alignment by bringing the residual portion into a channel.
According to each of the sixty-eighth, seventy-third and seventy-fourth aspects of the present invention, the channel is formed by a single-crystalline film, whereby it is possible to improve electron mobility in the channel to reduce the resistance value when the transistor is turned on, and an OFF-state current can be reduced by preventing occurrence of a leakage current by a regular crystal structure when the transistor is turned off.
According to each of the sixty-ninth, seventy-fifth and seventy-sixth aspects of the present invention, the gate insulating film is formed by a single-crystalline film, whereby it is possible to prevent occurrence of a leakage current and remarkably improve insulating the film withstand voltage.
According to each of the seventieth, seventy-seventh and seventy-eighth aspects of the present invention, the source and the drain are formed by single-crystalline films, whereby it is possible to reduce a leakage current which is caused by crystal defects.
According to each of the seventh-first, seventy-ninth and eightieth aspects of the present invention, the flattening film for an etchback operation and the second insulating film serving as an underlayer thereof have substantially equal degrees of crystallinity so that the etchback operation for flattening is carried out and a contact hole is formed through the upper surface of the flattening film and the second insulating film to reach the upper surface of the interconnection film in such a state, whereby the flattening film and the second insulating film are at the same etching rates in the etchback operation and formation of the contact hole to facilitate the etching operation.
According to each of the sixty-eighth, eighty-first and eighty-second aspects of the present invention, the gate insulating film is formed by a single-crystalline high dielectric film or a single-crystalline ferroelectric film, whereby the same can be increased in thickness as compared with a thermal oxide film of silicon or the like to be remarkably improved in insulating property.
According to each of the seventy-second and eighty-third aspects of the present invention, at least one layer of the collector, the base and the emitter is formed by a single-crystalline film, whereby it is possible to improve electron mobility and reduce the resistance when the transistor is turned on while occurrence of a leakage current can be prevented to suppress current consumption by regulating the crystal structure when the transistor is turned off. Namely, it is possible to provide a high characteristic semiconductor device having a high ON-OFF ratio of a collector current. Further, impurity activation can be carried out at a low temperature causing no impurity diffusion, whereby the thickness of the base or the emitter of the transistor or impurity concentration can be accurately controlled to reduce characteristic dispersion of the bipolar transistor.
According to each of the sixty-eighth to eighty-second aspects of the present invention, it is possible to easily form a single-crystalline thin film having a regulated crystal orientation on an arbitrary underlayer under a low temperature. According to each of the sixty-eighth, eighty-first and eighty-second aspects of the present invention, in particular, it is possible to form a homogeneous and stable single-crystalline film even if a constant thickness is required for the single-crystalline film.
According to the eighty-third aspect of the present invention, the formation layers can be activated with no high-temperature treatment and no impurity diffusion, whereby the thicknesses and activation characteristics of the formation layers can be accurately controlled to reduce characteristic dispersion of the semiconductor device. Further, at least one of the formation layers is so single-crystallized that electron mobility can be improved to reduce the resistance when the transistor is turned on while occurrence of a leakage current can be prevented to suppress current consumption by regulating the crystal structure when the transistor is turned off. Namely, it is possible to provide a high characteristic semiconductor device having a high ON-OFF ratio of a drain current.
According to each of the seventy-third, seventy-fourth, seventy-seventh and seventy-eighth aspects of the present invention, the regions for defining the source and the drain and the channel are simultaneously single-crystallized so that an impurity is introduced into the regions for defining the source and the drain through a mask of the gate, whereby it is possible to fabricate a semiconductor device having a single-crystalline structure in self alignment by bringing the residual portion into a channel.
Accordingly, an object of the present invention is to provide a semiconductor device which can simultaneously reduce the cost and improve transistor characteristics, and a method of fabricating the same.
Another object of the present invention is to provide a semiconductor device which can improve the quality of a gate oxide film while accurately controlling a threshold value at the same time, and a method of fabricating the same.
Still another object of the present invention is to provide a semiconductor device which can implement shallow junction through a treatment at a relatively low temperature of not more than 800xc2x0 C. while recovering defects caused in a source and a drain and activating an impurity, and a method of fabricating the same.
A further object of the present invention is to provide a semiconductor device which can attain sufficient reliability with reduction of fabrication steps, and a method of fabricating the same.
A further object of the present invention is to provide a semiconductor device which can implement flattening with an easy etchback operation, and a method of fabricating the same.
A further object of the present invention is to provide a semiconductor device which can remarkably improve the insulation property of a gate insulating film through a simple fabricating operation, and a method of fabricating the same.
A further object of the present invention is to provide a semiconductor device which can implement a finer bipolar transistor of higher performance and smaller characteristic dispersion as compared with a conventional transistor at a temperature of not more than 800xc2x0 C. causing no impurity diffusion, and a method of fabricating the same.
The step of crystallizing the prescribed material comprises: a step of depositing the prescribed material under a low temperature causing no crystallization of the prescribed material and simultaneously irradiating the prescribed material which is being deposited with a gas beam of low energy causing no sputtering of the prescribed material from one direction, thereby forming an axially oriented polycrystalline thin film; and a step of irradiating the axially oriented polycrystalline thin film with gas beams of low energy causing no sputtering of the prescribed material under a high temperature below a crystallization temperature of the prescribed material from different directions in the single-crystalline thin film to be formed which are perpendicular to the plurality of the densest crystal planes, thereby converting the polycrystalline thin film into a single-crystalline thin film.
In this case, even if the beams from the plurality of the directions fail to uniformly irradiate the substrate, it is possible to form either at least a single-crystalline thin film or an axially oriented polycrystalline thin film of the prescribed material on every portion of the substrate partly because the substrate has a cubic structure and partly because of other reasons. Further, since there is irradiation of the beams at least from one direction, it is possible to cause crystallization in a considerably large region including crystallization in the horizontal direction.
Alternatively, the step of crystallizing the prescribed material involves formation of a single-crystalline thin film semiconductor layer on the substrate and requires to form an amorphous thin film or a polycrystalline thin film of the semiconductor layer on the substrate in advance. This step is characterized in that gas beams of low energy causing no sputtering of the semiconductor layer are irradiated at a high temperature below a crystallization temperature of the semiconductor layer upon the amorphous or the polycrystalline thin film from different directions in the single-crystalline thin film to be formed which are perpendicular to the plurality of the densest crystal planes.
In this case, even if the beams from the plurality of the directions fail to uniformly irradiate the substrate, it is possible to form either at least a single-crystalline thin film or an axially oriented polycrystalline thin film of the prescribed material on every portion of the substrate partly because the substrate has a cubic structure and partly because of other reasons. Further, since there is irradiation of the beams at least from one direction, it is possible to cause crystallization in a considerably large region including crystallization in the horizontal direction.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.